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## US1050 Fiches technique(PDF) 6 Page - UNISEM

 No de pièce US1050 Description 5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR Download 7 Pages Scroll/Zoom 100% Fabricant UNISEM [UNISEM] Site Internet Logo

## US1050 Fiches technique(HTML) 6 Page - UNISEM

 6 / 7 pageUS10502-38Rev. 1.310/27/00The Sanyo MVGX series is a good choice to achieveboth price and performance goals.The 6MV1500GX ,1500uF, 6.3V has an ESR of less than 36 mΩ typ .Selecting 5 of these capacitors in parallel has an ESRof≈7.2 mΩ which achieves our design goal.The next step is to calculate the drop due to the capaci-tance discharge and make sure that this drop in voltageis less than the selected ESL drop in the previous step.2) The output capacitance is 5X1500 uF = 7500uFTo set the output DC voltage, we need to select R1 andR2 :3) Assuming R1=121Ω , 0.1%Select R2=218ΩΩ ,0.1%Selecting both R1 and R2 resistors to be 0.1% toler-ance, results in the least amount of error introduced bythe resistor dividers leaving≈ ±1.3% error budget forthe US1050 reference which is within the initial accu-racy of the device.Finally , the input capacitor is selected as follows :4) Assuming that the input voltage can drop 150mV be-fore the main power supply responds, and that the mainpower supply response time is≈ 50 uSec, then the mini-mum input capacitance for a 4.6A load step is given byoutput voltage of the regulator. As shown in this figure,the ESR of the output capacitor produces an instanta-neous drop equalto the (∆VESR=ESR*∆I) and the ESLeffect will be equal to the rate of change of the outputcurrent times the inductance of the capacitor. (∆VESL=L*∆I/∆t) . The output capacitance effect is a droop inthe output voltage proportional to the time it takes forthe regulator to respond to the change in the current ,(∆VC = ∆t * ∆I / C ) where ∆t is the response time of theregulator.Figure 4 - Typical Regulator response to the fast loadcurrent step.An example of a regulator design to meet the IntelP54C™ VRE specification is given below .Assume the specification for the processor as shown inTable 1:Type ofVoutImaxMax AllowedProcessorNominalOutput ToleranceIntel-P54C VRE3.50 V4.6 A±100 mVTable 1 - Processr SpecificationThe first step is to select the voltage step allowed in theoutput due to the output capacitor’s ESR :1) Assuming the regulator’s initial accuracy plus the re-sistor divider tolerance is≈ ±53 mV (±1.5% of 3.5V nomi-nal) ,then the total step allowed for the ESR and theESL, is−47 mV .Assuming that the ESL drop is−10mV ,the remainingESR step will be−37 mV . Therefore the output capaci-tor ESR must be :∆∆∆∆VtICWhere :the regulator response timeC=×= ×=2 4 6750012.. mV=2 uS is tRVVOUTREF211213 51251121 217 8=−×=−×=...ΩCIN=×=4 6 500 151530..FµV ESRV ESLV CTLOADCURRENTLOAD CURRENT RISE TIME1050plt1-1.0ESR≤=374 68.mΩ