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DM8203EP Fiches technique(PDF) 8 Page - Davicom Semiconductor, Inc. |
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DM8203EP Fiches technique(HTML) 8 Page - Davicom Semiconductor, Inc. |
8 / 63 page DM8203 2-port switch with MII / RMII Interface 8 Preliminary datasheet DM8203-15-DS-P05 October 23, 2008 1. General Description The DM8203 is a fully integrated, high performance, and cost-effective fast Ethernet switch controller, two ports 10M/100Mbps PHY, and one port MII, Reverse MII or RMII interface. The DM8203 with two ports 10M/100Mbps PHY, and one port MII, Reverse MII or RMII interface is a fully integrated, high performance, and cost-effective fast Ethernet switch controller The internal memory of the DM8203 supports up to 1K uni-cast MAC address table, it is provided for three ports’ usage. Each port of the DM8203 provides four priorities transmit queues that can be defined by port-based, 802.1p VLAN, or IP packet ToS field automatically, to fit the various bandwidth and latency requirement of data, voice, and video application. Besides, it’s internal memory has three ports usage, supporting up to 1K uni-case MAC address table. Each port of DM8203 provides four priorities transmit queens that can be defined by port-based, 802.1p VLAN, or IP packet ToS field automatically, applies to the various bandwidth and latency requirement of data, voice, and video application. Each port also supports ingress and/or egress rate control to provide proper bandwidth. And up to 16 groups of 802.1Q VLAN with Tag/Un-tag functions are supported to provide efficient packet forwarding. Each port, provide the MIB counters and loop-back capability and the build in memory self test (BIST) for system and board level diagnostic. For proper bandwidth, each port also supports ingress and/or egress rate control, and up to 16 groups of 802.1Q VLAN with Tag/Un-tag functions support packet forwarding efficiently. Each port provides the MIB counters, loop-back capability and the build in memory self test (BIST) for system and board level diagnostic. The integrated two ports PHY are compliant with IEEE 802.3u standards. The MII interface provides the flexibility to connect Ethernet PHY, and it can be configured to Reversed MII interface for SoC with MII interface. An alternative interface, the RMII interface, is also provided to connect the lower pin count Ethernet PHY or SoC with RMII interface. 2. Block Diagram 10/100M PHY 10/100M MAC 10/100M PHY 10/100M MAC 10/100M MAC Port 0 MDI / MDIX Port 1 MDI / MDIX Port 2 MII / RMII Switch Controller Control Registers MIB Counters EEPROM Interface Embedded Memory Memory BIST Memory Management Switch Engine LED Control LEDs EEPROM Switch Fabric SMI I/F / Reverse MII |
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