Rev 1.1, August 7, 2008

Page 8 of 12

SL38000

Programmable Output Clock (CLKOUT) Rise and Fall Times

The output clock rise and fall times (tr/tf) of each clock output can be programmed independently to match drive level

to load impedance.

Programming

Code

VDDO=3.3V

CL=15pF

VDDO=2.5V

CL=15pF

VDDO=1.8V

CL=15pF

Unit

000

4.00

4.80

5.60

ns

001

2.00

2.60

3.20

ns

010

1.40

1.80

2.20

ns

011

1.10

1.40

1.70

ns

100

0.85

1.10

1.40

ns

101

0.70

0.90

1.10

ns

110

0.55

0.70

0.90

ns

Table 1. Programmable CLKOUT Rise and Fall Times

Notes:

1. All typical values are at respective nominal VDD values.

2. The worst case rise and fall times variations are +/- 20% for C-Grade and +/-30% for I-grade.

I2C-Bus Timing Specifications

STANDARD-MODE

FAST-MODE

PARAMETER

SYMBOL

MIN.

MAX.

MIN.

MAX.

UNIT

SCL Clock

Frequency

0

100

0

400

kHz

START hold

time

4.0

-

0.6

-

μs

SCLK LOW

period

4.7

-

1.3

-

μs

SCLK HIGH

period

4.0

-

0.6

-

μs

START Set-

up time

4.7

-

0.6

-

μs

SDA set-up

time

250

-

100

-

ns

SDA/SCLK

rise time

-

1000

-

300

ns