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TA1322FN Fiches technique(PDF) 9 Page - Toshiba Semiconductor |
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TA1322FN Fiches technique(HTML) 9 Page - Toshiba Semiconductor |
9 / 21 page TA1322FN 2002-02-12 9 Bus Line Characteristics Parameter Symbol Test Circuit Test Condition Min Typ. Max Unit SCL clock frequency fSCL 0 ¾ 100 kHz Bus free time between a STOP and START conditions tBUF 4.7 ¾ ¾ ms Hold time for repeated START condition tHD; STA 4 ¾ ¾ ms SCL clock low period tLOW 4.7 ¾ ¾ ms SCL clock high period tHIGH 4 ¾ ¾ ms Set-up time for repeated START condition fSU; STA 4.7 ¾ ¾ ms Data hold time tHD; DAT 0 ¾ ¾ ms Data set-up time tSU; DAT 250 ¾ ¾ ns Rise time for SDA and SCL signals tR ¾ ¾ 1000 ns Fall time for SDA and SCL signals tF ¾ ¾ 300 ns Set-up time for STOP condition tsU; STO ¾ Please refer to data timing chart. 4 ¾ ¾ ms tHD; STA tSU; STO SDA SCL tBUF tLOW tR tF tHD; STA tHD; DAT tHIGH tSU; DAT tSU; STA P S Sr P Figure 1 I 2 C Bus Data Timing Chart (rising-edge timing) |
Numéro de pièce similaire - TA1322FN |
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