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TPS65720YFFR Fiches technique(PDF) 4 Page - Texas Instruments |
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TPS65720YFFR Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 50 page TPS65720 TPS65721 SLVS979 – OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SDAT, SCLK, PB_IN, HOLD, GPIO0 TO GPIO3, INT, RESET, THRESHOLD High level input voltage for SCLK, SDAT, GPIOx, VIH GPIOs configured as input 1.2 VSYS V HOLD_DCDC1, HOLD_LDO1, PB_IN Low level input voltage for SCLK, SDAT, GPIOx, VIL GPIOs configured as input 0 0.4 V HOLD_DCDC1, HOLD_LDO1, PB_IN Low level output voltage for SDAT, GPIOx, INT, VOL GPIOs configured as output; Io=1mA; no internal pull-up 0 0.4 V RESET GPIO2, GPIO3 configured as current sink; VOL=0.4V ; for Sink current for GPIO2, GPIO3 –20% 5 20% mA Tj=0°C to 85°C IOL Sink current for GPIOx GPIOx configured as open drain output ; output = LOW 3 mA Minimum voltage for proper current regulation from VOL GPIO2 or GPIO3 to GND if programmed as a Io=5mA; current sink turned on 0.4 V current sink VLDO1, VLDO1, VRESET-falling Falling edge; Reset is asserted LOW for TPS65720 V nom-13% nom-7% LDO1 out of regulation reset voltage Rising edge; Reset is released HIGH for TPS65720 after VLDO1, VRESET-rising V TRESET nom-4% Low to high transition of RESET pin, depending on setting of 9 11 13 ms Bit RESET_DELAY 70 90 110 TRESET Reset delay time on pin RESET HIGH to LOW transition of RESET pin RESET will go low by HOLD pin going LOW AND HOLD Bit set to 0 OR voltage at 10 μs Vreset falling below the threshold VTHRESHOLD_down Threshold voltage for reset input Falling voltage; QFN package only –3% 570 3% mV VTHRESHOLD_hys Hysteresis on THRESHOLD Rising voltage; QFN package only 30 mV Tdebounce Debounce time at PB_IN Rising and falling voltage 39 50 60 ms PB_IN, SDAT, SCLK, GPIOx configured as output, INT, ILKG Input leakage current 0.2 μA RESET, output high impedance STEP-DOWN CONVERTER VSYS Input voltage for DCDC1 2.3 5.6 V VSYS falling 2.15 2.2 2.25 V UVLO Internal undervoltage lockout threshold hysteresis VSYS rising 120 mV POWER SWITCH VSYS = VINDCDC1 = 3.6V, YFF package 350 600 RDS(ON) High side MOSFET on-resistance m Ω VSYS = VINDCDC1 = 3.6V, RSN package 400 650 ILK_HS High side MOSFET leakage current VDS = 5.6V 1 μA VINDCDC1/2 = 3.6 V, YFF package 300 500 m Ω RDS(ON) Low side MOSFET on-resistance VINDCDC1/2 = 3.6 V, RSN package 350 550 m Ω ILK_LS Low side MOSFET leakage current VDS = 5.6 V 1 μA 2.3 V ≤ VIN ≤ 5.6 V, TPS65720 425 600 775 mA Forward current limit high-side and low side ILIMF MOSFET 2.3 V ≤ VIN ≤ 5.6 V, TPS65721 625 850 1150 mA VSYS > 2.7 V; TPS65720 200 Io DC output current mA VSYS > 2.7 V ; TPS65721 400 OSCILLATOR fSW Oscillator Frequency 2.03 2.25 2.48 MHz OUTPUT VOUT Output Voltage Range 0.6 Vin V VFB Feedback voltage 0.6 V IFB FB pin input current 0.1 μA VIN = 2.3 V to 5.6 V; PFM operation, 0 mA < IOUT < IOUTMAX 1% 3% DC Output voltage accuracy (1) VOUT VIN = 2.3 V to 5.6 V, PWM operation, 0 mA < IOUT < IOUTMAX –2% 2% DC output voltage load regulation PWM operation 0.5 %/A VDCDC1, VDCDC1, VPGOOD-falling PGOOD threshold at falling output voltage <PGOODZ_DCDC1> is set to 1 V nom-14% nom-7% VDCDC1, VPGOOD-rising PGOOD threshold at rising output voltage <PGOODZ_DCDC1> is set to 0 V nom-5% tStart Start-up time Time from active EN to Start switching 170 μs tRamp VOUT ramp time Time to ramp from 5% to 95% of VOUT 250 μs (1) Output voltage specification does not include tolerance of external voltage programming resistors 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65720 TPS65721 |
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