TPS54318

The TPS54318 reduces the external component count by integrating the boot recharge diode. The bias voltage

for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor

voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a

preset threshold. This BOOT circuit allows the TPS54318 to operate approaching 100%. The output voltage can

be stepped down to as low as the 0.8 V reference.

The TPS54318 has a power good comparator (PWRGD) with 2% hysteresis.

The TPS54318 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power

good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the

overvoltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until

the output voltage is lower than 105%.

The SS (slow start) pin is used to minimize inrush currents or provide power supply sequencing during power up.

A small value capacitor should be coupled to the pin for slow start. The SS pin is discharged before the output

power up to ensure a repeatable restart after an over-temperature fault, UVLO fault or disabled condition.

The use of a frequency foldback circuit reduces the switching frequency during startup and over current fault

conditions to help limit the inductor current.

DETAILED DESCRIPTION

FIXED FREQUENCY PWM CONTROL

The TPS54318 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared

through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives

the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output

is compared to the high side power switch current. When the power switch current reaches the COMP voltage

level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage

increases and decreases as the output current increases and decreases. The device implements a current limit

by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved

transient response performance.

SLOPE COMPENSATION AND OUTPUT CURRENT

The TPS54318 adds a compensating ramp to the switch current signal. This slope compensation prevents

sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the

full duty cycle range.

BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION

The TPS54318 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and

PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be

0.1

μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is

recommended because of the stable characteristics over temperature and voltage.

To improve drop out, the TPS54318 is designed to operate at 100% duty cycle as long as the BOOT to PH pin

voltage is greater than 2.5 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low

side MOSFET to conduct when the voltage from BOOT to PH drops below 2.5 V. Since the supply current

sourced from the BOOT pin is low, the high side MOSFET can remain on for more switching cycles than are

required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high.

ERROR AMPLIFIER

The TPS54318 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower

of the SS pin voltage or the internal 0.8 V voltage reference. The transconductance of the error amplifier is

225

μA/V during normal operation. When the voltage of VSENSE pin is below 0.8 V and the device is regulating

using the SS voltage, the gm is 70

μA/V. The frequency compensation components are placed between the

COMP pin and ground.

Copyright © 2009, Texas Instruments Incorporated

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