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TC74VHC139FK Fiches technique(PDF) 1 Page - Toshiba Semiconductor |
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TC74VHC139FK Fiches technique(HTML) 1 Page - Toshiba Semiconductor |
1 / 9 page TC74VHC139F/FN/FT/FK 2008-05-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC139F,TC74VHC139FN,TC74VHC139FT,TC74VHC139FK Dual 2-to-4 Line Decoder The TC74VHC139 is an advanced high speed CMOS 2 to 4 LINE DECODER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The active low enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held High, all four outputs are fixed at a high logic level independent of the other inputs. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features • High speed: tpd = 5.0 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Power down protection is provided on all inputs. • Balanced propagation delays: tpLH ≈ tpHL • Wide operating voltage range: VCC (opr) = 2 V to 5.5 V • Pin and function compatible with 74ALS139 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74VHC139F TC74VHC139FN TC74VHC139FT TC74VHC139FK Weight SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) VSSOP16-P-0030-0.50 : 0.02 g (typ.) (top view) VCC 16 2A 2B 15 14 13 12 11 10 1 2 3 4 5 6 7 GND 8 9 1A 1B G 1 0 Y 1 1 Y 1 2 Y 1 3 Y 1 G 2 0 Y 2 1 Y 2 2 Y 2 3 Y 2 |
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