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CS5560 Fiches technique(PDF) 8 Page - Cirrus Logic |
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CS5560 Fiches technique(HTML) 8 Page - Cirrus Logic |
8 / 32 page CS5560 8 DS713PP2 5/4/09 SWITCHING CHARACTERISTICS (CONTINUED) TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF. 12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor. 13. SCLK = MCLK/2. Parameter Symbol Min Typ Max Unit Serial Port Timing in SSC Mode (SMODE = VL) Data hold time after SCLK rising t7 -10 - ns Serial Clock (Out) Pulse Width (low) (Note 12, 13) Pulse Width (high) t8 t9 50 50 - - - - ns ns RDY rising after last SCLK rising t10 -8 - MCLKs CS falling to MSB stable t11 -10 - ns First SCLK rising after CS falling t12 -8 - MCLKs CS hold time (low) after SCLK rising t13 10 - - ns SCLK, SDO tristate after CS rising t14 -5 - ns MCLK RDY SCLK(o) SDO CS t12 t8 t13 t9 t7 t11 MSB MSB–1 LSB LSB+1 t14 t10 Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale) |
Numéro de pièce similaire - CS5560 |
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Description similaire - CS5560 |
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