TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

5

POST OFFICE BOX 655303

timing diagram

† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

VI

Vres†

Vres

t

t

t

VO

Threshold

Voltage

RESET

Output

200 ms

Delay

200 ms

Delay

Output

Undefined

Output

Undefined

VIT +‡

VIT –‡

VIT –‡

VIT +‡

Less than 5% of the

output voltage

‡ VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT–

to VIT+ is the hysteresis voltage.