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TMS320UVC5402 Fiches technique(PDF) 42 Page - Texas Instruments |
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TMS320UVC5402 Fiches technique(HTML) 42 Page - Texas Instruments |
42 / 60 page TMS320UVC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS100A – APRIL 1999 – REVISED AUGUST 1999 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HOLD and HOLDA timings switching characteristics over recommended operating conditions for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 17) PARAMETER MIN MAX UNIT tdis(CLKL-A) Disable time, address, PS, DS, IS high impedance from CLKOUT low 2 ns tdis(CLKL-RW) Disable time, R/W high impedance from CLKOUT low 2 ns tdis(CLKL-S) Disable time, MSTRB, IOSTRB high impedance from CLKOUT low 2 ns ten(CLKL-A) Enable time, address, PS, DS, IS from CLKOUT low 2H+10 ns ten(CLKL-RW) Enable time, R/W enabled from CLKOUT low 2H+10 ns ten(CLKL-S) Enable time, MSTRB, IOSTRB enabled from CLKOUT low 2 2H+10 ns t Valid time, HOLDA low after CLKOUT low 0 10 ns tv(HOLDA) Valid time, HOLDA high after CLKOUT low –2 8 ns tw(HOLDA) Pulse duration, HOLDA low duration 2H–3 ns timing requirements for memory control signals and HOLDA, [H = 0.5 tc(CO)] (see Figure 17) MIN MAX UNIT tw(HOLD) Pulse duration, HOLD low 4H+10 ns tsu(HOLD) Setup time, HOLD low/high before CLKOUT low 15 ns IOSTRB MSTRB R/W D[15:0] PS, DS, IS A[19:0] HOLDA HOLD CLKOUT ten(CLKL-S) ten(CLKL-S) ten(CLKL-RW) tdis(CLKL-S) tdis(CLKL-S) tdis(CLKL-RW) tdis(CLKL-A) tv(HOLDA) tv(HOLDA) tw(HOLDA) tw(HOLD) tsu(HOLD) tsu(HOLD) ten(CLKL-A) Figure 17. HOLD and HOLDA Timings (HM = 1) |
Numéro de pièce similaire - TMS320UVC5402 |
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Description similaire - TMS320UVC5402 |
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