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TL16PC564BPZ Fiches technique(PDF) 10 Page - Texas Instruments

No de pièce TL16PC564BPZ
Description  PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
Download  33 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TL16PC564BPZ Fiches technique(HTML) 10 Page - Texas Instruments

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TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
host CPU/UART interface
The UART select is derived from either host CPU address information or logic levels on CE1, CE2 and REG.
In the address mode, host CPU address bits HA9, HA7, HA6, HA5, and HA3 are combined with conditional
derivatives of HA4 and HA8 to select the UART (HA4 and HA8 select COM ports 1 – 4 based on settings in the
subsystem control register). CE1 and CE2 are combined such that either of these two signals in combination
with REG enable the UART in the event that these signals are present. In the event that CE1 or CE2 are not
present, the UART must be accessed in the address mode previously described. The UART select in
conjunction with IORD and IOWR allows host CPU accesses to the UART. Host CPU address bits HA2–HA0
are decoded to select which UART register is to be accessed.
All UART registers remain intact with the exception of the FIFO control register (FCR) and the modem-control
register (MCR). The FCR (host CPU write-only address 2) bits 4 and 5 in conjunction with EXTEND control RTS
operation and FIFO depth as follows:
BIT 5
BIT 4
EXTEND
RTS OPERATION
FIFO DEPTH
X
X
H
Normal
16 bytes
0
0
L
Normal
16 bytes
0
1
L
Auto
16 bytes
1
0
L
Normal
64 bytes
1
1
L
Auto
64 bytes
FCR bit 5 high and EXTEND low redefine the receiver FIFO trigger levels set by FCR bits 6 and 7 as follows:
BIT 7
BIT 6
TRIGGER LEVEL
0
0
1
0
1
16
1
0
32
1
1
56
The MCR (host CPU address 4) bit 5 is read only. Bit 5 is controlled by the subsystem to enable (high) the
auto-CTS mode of operation
subsystem/UART interface
The UART provides a serial-communications channel to the subsystem with enhanced RTS control (see
auto-RTS description). This channel is capable of operating at 115 kbps and is the main communications
channel to the subsystem (refer to the TL16C550 specification for the detailed description of the
serial-communications channel).
Many of the UART registers have been mapped into the subsystems memory space as read only. In addition,
MCR bit 5 (subsystem address 130 hex) is controlled by the subsystem to enable (high) auto-CTS. The
subsystem can read the MCR at address 134 hex. When reading the FCR (subsystem address 132 hex), bits
1 and 2 are always high, and bits 4 and 5 are low only when EXTEND is low and the host CPU has set them
high (64-byte FIFOs and auto-RTS enabled) (refer to the subsystem memory map).


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