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TCM29C13 Fiches technique(PDF) 10 Page - Texas Instruments |
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TCM29C13 Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 25 page TCM29C13, TCM29C14, TCM29C16, TCM29C17, TCM129C13, TCM129C14, TCM129C16, TCM129C17 COMBINED SINGLE-CHIP PCM CODEC AND FILTER SCTS011H – APRIL 1986 – REVISED JULY 1996 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 receive filter transfer over recommended ranges of supply voltage and operating free-air temperature (see Figure 2) PARAMETER TEST CONDITIONS MIN MAX UNIT f < 200 Hz 0.15 f = 200 Hz – 0.5 0.15 f = 300 Hz to 3 kHz – 0.15 0.15 Gain relative to gain at 1.02 kHz Input signal at PCM IN is 0 dBm0 f = 3.3 kHz – 0.35 0.15 dB f = 3.4 kHz –1 – 0.1 f = 4 kHz –14 f w 4.6 kHz –30 timing requirements clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 3 and 4) MIN TYP† MAX UNIT tc(CLK) Clock period for CLKX, CLKR (2.048-MHz systems) 488 ns tr, tf Rise and fall times for CLKX and CLKR 5 30 ns tw(CLK) Pulse duration for CLKX and CLKR (see Note 7) 220 ns tw(DCLK) Pulse duration, DCLK (fDCLK = 64 kHz to 2.048 MHz) (see Note 7) 220 ns Clock duty cycle, [tw(CLK)/tc(CLK)] for CLKX and CLKR 45% 50% 55% † All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25°C. NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR. transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 3) MIN MAX UNIT td(FSX) Frame-sync delay time 100 tc(CLK) – 100 ns tsu(SIGX) Setup time before bit 7 falling edge of CLKX (TMC29C14 and TCM129C14 only) 0 ns th(SIGX) Hold time after bit 8 falling edge of CLKX (TCM29C13 and TCM129C14 only) 0 ns receive timing requirements over recommended ranges of supply voltages and operating free-air temperature, fixed-data-rate mode (see Figure 4) PARAMETER MIN MAX UNIT td(FSR) Frame-sync delay time 100 tc(CLK)–100 ns tsu(PCM IN) Setup time before bit 1 falling edge (TCM129C14 and TCM29C14 only) 10 ns th(PCM IN) Hold time after bit 1 falling edge (TCM129C14 and TCM29C14 only) 60 ns transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 5) PARAMETER MIN MAX UNIT td(TSDX) Time-slot delay time from DCLKX (see Note 8) 140 td(DCLKX)–140 ns td(FSX) Frame-sync delay time 100 tc(CLK)–100 ns tc(DCLKX) Clock period for DCLKX 488 15620 ns NOTE 8: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation. |
Numéro de pièce similaire - TCM29C13 |
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Description similaire - TCM29C13 |
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