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SN74GTLPH16612DL Fiches technique(PDF) 8 Page - Texas Instruments |
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SN74GTLPH16612DL Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 11 page SN74GTLPH16612 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER SCES326 – MARCH 2000 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) (see Figure 2) MIN MAX UNIT fclock Clock frequency 85 MHz t Pulse duration LEAB or LEBA high 3.3 ns tw Pulse duration CLKAB or CLKBA high or low 5.7 ns A before CLKAB ↑ 1 B before CLKBA ↑ 1.8 t Setup time A before LEAB ↓ 0.5 ns tsu Setup time B before LEBA ↓ 1.2 ns CEAB before CLKAB ↑ 1.2 CEBA before CLKBA ↑ 1.4 A after CLKAB ↑ 1.9 B after CLKBA ↑ 0.5 th Hold time A after LEAB ↓ 2.7 ns th Hold time B after LEBA ↓ 3.5 ns CEAB after CLKAB ↑ 1.2 CEBA after CLKBA ↑ 1.1 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP† MAX UNIT fmax 85 MHz A 2.5 6.9 tpd LEAB B 3.2 7.3 ns CLKAB 3.4 7.8 ten OEAB B 2.8 7 ns tdis OEAB B 2.8 7 ns tr Transition time, B outputs (20% to 80%) 2.6 ns tf Transition time, B outputs (80% to 20%) 2.6 ns B 1.5 5.7 tpd LEBA A 1.8 5.7 ns CLKBA 2.3 5.5 ten OEBA A 1.8 6.1 ns tdis OEBA A 1.8 6.1 ns † All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. |
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Description similaire - SN74GTLPH16612DL |
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