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SN74ACT3638PCB Fiches technique(PDF) 10 Page - Texas Instruments |
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SN74ACT3638PCB Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 30 page SN74ACT3638 512 × 32 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS228D – JUNE 1992 – REVISED APRIL 1998 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input-ready flags (IRA, IRB) The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array. When the input-ready flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the input-ready flag is low and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready flag is low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after the read sets the input-ready flag high. A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 9 and 10). ready flags (RDYA, RDYB) A ready flag is provided on each port to show if the transmitting or receiving FIFO chosen by the port write/read select is available for data transfer. The port-A ready flag (RDYA) outputs the complement of the IRA flag when W/RA is high and the complement of the ORA flag when W/RA is low. The port-B ready flag (RDYB) outputs the complement of the IRB flag when W/RB is low and the complement of the ORB flag when W/RB is high (see Figures 11 and 12). almost-empty flags (AEA, AEB) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset programming). A FIFO is almost empty when it contains X or fewer words in memory and is no longer almost empty when it contains (X + 1) or more words. Note that a data word present in the FIFO output register has been read from memory. Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14). almost-full flags (AFA, AFB) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The almost-full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset programming). A FIFO is almost full when it contains (512 – Y) or more words in memory and is not almost full when it contains [512 – (Y + 1)] or fewer words. A data word present in the FIFO output register has been read from memory. almost-full flags (AFA, AFB) (continued) Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [512 – (Y + 1)] or fewer words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [512 – (Y + 1)]. An almost-full flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [512 – (Y + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization |
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