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SN65LVDS1050 Fiches technique(PDF) 1 Page - Texas Instruments |
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SN65LVDS1050 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 17 page SN65LVDS1050 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS343A – APRIL 1999 – REVISED MARCH 2000 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Typically Meets or Exceeds ANSI TIA/EIA-644-1995 Standard D Operates From a Single 2.4-V to 3.6-V Supply D Signaling Rates up to 400 Mbit/s D Bus-Terminal ESD Exceeds 12 kV D Low-Voltage Differential Signaling With Typical Output Voltages of 285 mV and a 100 Ω Load D Propagation Delay Times – Driver: 1.7 ns Typ – Receiver: 3.7 ns Typ D Power Dissipation at 200 MHz – Driver: 25 mW Typical – Receiver: 60 mW Typical D LVTTL Input Levels Are 5 V Tolerant D Driver Is High Impedance When Disabled or With VCC < 1.5 V D Receiver Has Open-Circuit Fail Safe D Available in Thin Shink Outline Packaging With 20-mil Lead Pitch description The SN65LVDS1050 is similar to the SN65LVDS050 except that it is characterized for operation with a lower supply voltage range and packaged in the thin shrink outline package for portable battery-powered applications. The differential line drivers and receivers use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The drivers provide a minimum differential output voltage magnitude of 247 mV into a 100- Ω load and receipt of 100-mV signals with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100- Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment and other application-specific characteristics. The SN65LVDS1050 is characterized for operation from –40 °C to 85°C. Copyright © 2000, Texas Instruments Incorporated 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1B 1A 1R RE 2R 2A 2B GND VCC 1D 1Y 1Z DE 2Z 2Y 2D SN65LVDS1050PW (Marked as DL1050 or DLS1050) (TOP VIEW) 2D 1D 1Y 1Z 2Y 2Z DE 9 15 12 14 13 10 11 2R 1R 1A 1B 2A 2B RE 5 3 4 2 1 6 7 DRIVER FUNCTION TABLE RECEIVER FUNCTION TABLE INPUTS OUTPUTS INPUTS OUTPUT D X DE Y X VID = VA – VB VID ≥ 100 mV –100 MV < VID < 100 mV VID ≤ –100 mV Open RE R L Open Z L L L H H ? L H Z Z LL HH H H L H Z L HH L H = high level, L = low level, Z = high impedance, X = don’t care H = high level, L = low level, Z = high impedance, X = don’t care PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. |
Numéro de pièce similaire - SN65LVDS1050 |
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Description similaire - SN65LVDS1050 |
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