SN54GTL16622A, SN74GTL16622A

18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS

SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999

9

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR A OUTPUTS

S1

6 V

Open

GND

500

Ω

500

Ω

TEST

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

S1

Open

6 V

GND

tPLH

tPHL

Output

Control

(see Note B)

Output

Waveform 1

S1 at 6 V

(see Note C)

Output

Waveform 2

S1 at GND

(see Note C)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

3 V

0 V

VREF

VREF

VOH

VOL

0 V

VOL + 0.3 V

VOH – 0.3 V

≈0 V

3 V

0 V

0 V

3 V

0 V

tw

Input

(see Note B)

3 V

3 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(CLKAB to B port)

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

(OEBA to A port)

Timing

Input

Data Input

A Port

Output

Input

VTT

Test

Point

CL = 30 pF

(see Note A)

From Output

Under Test

25

Ω

LOAD CIRCUIT FOR B OUTPUTS

tPLH

tPHL

0 V

VOH

VOL

Input

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

(CLKBA to A port)

Output

3 V

VREF

VREF

0 V

VTT

Data Input

B Port

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. The outputs are measured one at a time with one transition per measurement.

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

1.5 V

Figure 1. Load Circuits and Voltage Waveforms