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SN74GTL16612ADGG Fiches technique(PDF) 8 Page - Texas Instruments |
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SN74GTL16612ADGG Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 15 page www.ti.com PARAMETER MEASUREMENT INFORMATION th tsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS S1 6 V Open GND 500 Ω 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6 V GND tPLH tPHL Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 3 V 0 V VREF VREF VTT VOL 0 V VOL + 0.3 V VOH − 0.3 V ≈0 V 3 V 0 V 0 V 3 V 0 V tw Input 3 V 3 V 3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) Timing Input Data Input A Port Output Input VTT Test Point CL = 30 pF (see Note A) From Output Under Test 25 Ω LOAD CIRCUIT FOR B OUTPUTS tPLH tPHL 0 V VOH VOL Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) Output VTT VREF VREF VREF VREF 0 V VTT Data Input B Port NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V SN54GTL16612A, SN74GTL16612A 18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS SCES187D – JANUARY 1999 – REVISED JULY 2005 Figure 2. Load Circuits and Voltage Waveforms 8 |
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