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SN74ALS996DW Fiches technique(PDF) 4 Page - Texas Instruments |
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SN74ALS996DW Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 9 page SN54ALS996, SN74ALS996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions SN54ALS996 SN74ALS996 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V All inputs 2 VIH High-level input voltage All inputs except OE, RD 2 V OE, RD 2.2 VIL Low-level input voltage 0.8 0.8 V IOH High level output current Q –1 – 2.6 mA IOH High-level output current D – 0.4 – 0.4 mA Q 12 24 IOL Low-level output current Q 48† mA D 8 8 fclock Clock frequency 0 35 0 35 MHZ CLR low 10 10 tw Pulse duration CLK low 14.5 14.5 ns CLK high 14.5 14.5 Data before CLK ↑ 15 15 t Setup time EN low before CLK ↑ 10 10 ns tsu Setup time CLK high before EN ↑‡ 15 15 ns CLR high (inactive) before CLK ↑ 10 10 Data after CLK ↑ 1 0 th Hold time EN low after CLK ↑ 5 5 ns RD high after CLK ↑§ 5 5 TA Operating free-air temperature –55 125 0 70 °C † Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V ‡ This setup time ensures that EN will not false clock the data register. § This hold time ensures that there will be no conflict on the input data bus. |
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Description similaire - SN74ALS996DW |
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