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SN54ABT651 Datasheet(Fiches technique) 1 Page - Texas Instruments

Numéro de pièce SN54ABT651
Description  OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
Télécharger  11 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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SN54ABT651, SN74ABT651
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS083E – JANUARY 1991 – REVISED APRIL 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D High-Drive Outputs (–32-mA IOH,
64-mA IOL)
D Multiplexed Real-Time and Stored Data
D Inverting Data Paths
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. The
select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. A low input level selects real-time
data, and a high input level selects stored data.
Figure
1
illustrates
the
four
fundamental
bus-management
functions
that
can
be
performed with the ’ABT651 devices.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all
the other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Copyright
© 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-
ΙΙB is a trademark of Texas Instruments Incorporated.
SN54ABT651 . . . FK PACKAGE
(TOP VIEW)
SN54ABT651 . . . JT PACKAGE
SN74ABT651 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
32 1
13 14
5
6
7
8
9
10
11
OEBA
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
4
15 16 17 18
28 27 26
12
NC – No internal connection
25
24
23
22
21
20
19




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