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CDCVF2509 Fiches technique(PDF) 6 Page - Texas Instruments |
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CDCVF2509 Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 11 page CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS637 – DECEMBER 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note 6 and Figures 1 and 2)‡ PARAMETER FROM (INPUT)/CONDITION TO (OUTPUT) VCC, AVCC = 3.3 V ± 0.3 V UNIT (INPUT)/CONDITION (OUTPUT) MIN TYP MAX Phase error time – static (normalized) (see Figures 3 – 6) CLK ↑ = 66 MHz to166 MHz FBIN ↑ –125 125 ps tsk(o) Output skew time§ Any Y Any Y 100 ps Phase error time – jitter (see Note 7) CLK = 66 MHz to 166 MHz Any Y or FBOUT –50 50 Jitter(cycle-cycle) Any Y or FBOUT |70| ps (cycle cycle) (see Figure 7) CLK = 100 MHz to 166 MHz Any Y or FBOUT |65| Duty cycle f(CLK) > 60 MHz Any Y or FBOUT 45% 55% tr Rise time VO = 0.4 V to 2 V Any Y or FBOUT 0.5 2.5 ns/V tf Fall time VO = 0.4 V to 2 V Any Y or FBOUT 0.5 2.5 ns/V tPLH(bypass mode) Low-to-high propagation delay time, bypass mode CLK Any Y or FBOUT 0.4 2.3 ns tPHL(bypass mode) High-to-low propagation delay time, bypass mode CLK Any Y or FBOUT 0.4 2.3 ns ‡ These parameters are not production tested. § The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 7. Calculated per PC DRAM SPEC (tphase error, static – jitter(cycle-to-cycle)). |
Numéro de pièce similaire - CDCVF2509 |
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Description similaire - CDCVF2509 |
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