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CD74HC175 Datasheet(Fiches technique) 6 Page - Texas Instruments

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Numéro de pièce CD74HC175
Description  High Speed CMOS Logic Quad D-Type Flip-Flop with Reset
Télécharger  7 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

CD74HC175 Datasheet(HTML) 6 Page - Texas Instruments

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6
HCT TYPES
Propagation Delay,
Clock to Q or Q
tPLH, tPHL
CL = 50pF
4.5
-
33
41
50
ns
CL = 15pF
5
13
-
-
-
ns
Propagation Delay,
MR to Q or Q
tPLH, tPHL
CL = 50pF
4.5
-
35
44
53
ns
CL = 15pF
5
17
-
-
-
ns
Output Transition Times
tTLH, tTHL
CL = 50pF
4.5
-
15
19
22
ns
Input Capacitance
CIN
--
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 6, 7)
CPD
-
5
67
-
-
-
pF
NOTES:
6. CPD is used to determine the dynamic power consumption, per flip-flop.
7. PD =VCC
2 f
i + ∑ (CL VCC
2 +f
O) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oC TO 85oC
-55oC TO
125oC
UNITS
TYP
MAX
MAX
MAX
Test Circuits and Waveforms
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
trCL
tfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC
50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH
tTHL
tH(L)
tPHL
IC
CL
50pF
tSU(L)
tH(H)
trCL
tfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V
1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH
tTHL
tH(L)
tPHL
IC
CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD74HC175, CD74HCT175


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