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TC850CLW Fiches technique(PDF) 4 Page - TelCom Semiconductor, Inc |
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TC850CLW Fiches technique(HTML) 4 Page - TelCom Semiconductor, Inc |
4 / 14 page 3-80 TELCOM SEMICONDUCTOR, INC. 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER TC850 PIN DESCRIPTIONS 40-Pin DIP Pin No. Symbol Description 1 CS Chip select, active HIGH. Logically ANDed with CE to enable read and write inputs. (See note 4.) 2 CE Chip enable, active LOW. (See note 5.) 3 WR Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and in demand mode (CONT/DEMAND = LOW), a logic LOW on WR starts a conversion. (See note 4.) 4 RD Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD enables the 3-state data outputs. (See note 5.) 5 CONT/DEMAND Conversion control input. When CONT/DEMAND = LOW, conversions are initiated by the WR input. When CONT/DEMAND = HIGH, conversions are performed continuously. (See note 4.) 6 OVR/POL Overrange/polarity data-select input. When making conversions in the demand mode (CONT/ DEMAND = LOW), OVR/POL controls the data output on DB7 when the high-order byte is active. (See note 5.) 7 L/H Low/high byte-select input. When CONT/DEMAND = LOW, this input controls whether low- byte or high-byte data is enabled on DB0 through DB7. (See note 5.) 8 DB7 Most significant data bit output. When reading the A/D conversion result, the polarity, overrange, and DB7 data are output on this pin. (See text.) 9 – 15 DB6–DB0 Data outputs DB6–DB0. 3-state, bus compatible. 16 BUSY A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the deintegrate phase and goes LOW when conversion is complete. The falling edge of BUSY can be used to generate a µP interrupt. 17 OSC1 Crystal oscillator connection or external oscillator input. 18 OSC2 Crystal oscillator connection. 19 TEST For factory testing purposes only. Do not make external connection to this pin. 20 DGND Digital ground connection. 21 COMP Connection for comparator auto-zero capacitor. Bypass to VSS with 0.1 µF. 22 VSS Negative power supply connection, typically – 5V. 23 INTOUT Output of the integrator amplifier. Connect to CINT. 24 INTIN Input to the integrator amplifier. Connect to summing node of RINT and CINT. 25 BUFFER Output of the input buffer. Connect to RINT. 26 CBUFB Connection for buffer auto-zero capacitor. Bypass to VSS with 0.1 µF. 27 CBUFA Connection to buffer auto-zero capacitor. Bypass to VSS with 0.1 µF. 28 CINTA Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 µF. 29 CINTB Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 µF. 30 COMMON Analog common. 31 IN– Negative differential analog input. 30 COMMON Analog common. 33 REF2+ Positive input for reference voltage VREF2. (VREF2 = VREF1/64) 34 CREF2+ Positive connection for VREF2 reference capacitor. 35 CREF2– Negative connection for VREF2 reference capacitor. 36 REF – Negative input for reference voltages. 37 CREF1– Negative connection for VREF1 reference capacitor. 38 CREF1+ Positive connection for VREF1 reference capacitor. 39 REF1+ Positive input for VREF1. 40 VDD Positive power supply connection, typically +5V. NOTES: 4. This pin incorporates a pull-down resistor to DGND. 5. This pin incorporates a pull-up resistor to VDD. |
Numéro de pièce similaire - TC850CLW |
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Description similaire - TC850CLW |
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