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TCA4311DR Fiches technique(PDF) 6 Page - Texas Instruments

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No de pièce TCA4311DR
Description  HOT SWAPPABLE 2-WIRE BUS BUFFERS
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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TCA4311DR Fiches technique(HTML) 6 Page - Texas Instruments

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OPERATION
Start-Up
Connection Circuitry
Input to Output Offset Voltage
Propagation Delays
TCA4311
SCPS173 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
When the TCA4311 first receives power on its VCC pin, either during power-up or during live insertion, it starts in
an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above
2.5 V.
During this time, the 1 V precharge circuitry is also active and forces 1 V through 100-k
Ω nominal resistors to the
SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane
SDA and SCL busses may be anywhere between 0 V and VCC. Precharging the SCL and SDA pins to 1 V
minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore
minimizing the amount of disturbance caused by the I/O card.
Once the TCA4311 comes out of UVLO, it assumes that SDAIN and SCLIN have been inserted into a live
system and that SDAOUT and SCLOUT are being powered up at the same time as itself. Therefore, it looks for
either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction.
When either one occurs, the part also verifies that both the SDAOUT and SCLOUT voltages are high. When all
of these conditions are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses
on the I/O card with those on the backplane, and the rise time accelerators are enabled.
Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages being low. For proper operation, logic low input
voltages should be no higher than 0.4 V with respect to the ground pin voltage of the TCA4311. SDAIN and
SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is
true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization,
arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to
the TCA4311.
Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as described here.
When a logic low voltage, VLOW1, is driven on any of the TCA4311's data or clock pins, the TCA4311 regulates
the voltage on the other side of the chip (call it VLOW2) to a slightly higher voltage, as directed by the following
equation:
VLOW2 = VLOW1 + 75 mV + (VCC/R) × 100
where R is the bus pullup resistance in ohms (
Ω). For example, if a device is forcing SDAOUT to 10 mV where
VCC = 3.3 V and the pullup resistor R on SDAIN is 10 kΩ, then the voltage on SDAIN = 10 + 75 + (3.3/10000) ×
100 = 118 mV. See the Typical Performance Characteristics section for curves showing the offset voltage as a
function of VCC and R.
During a rising edge, the rise-time on each side is determined by the combined pullup current of the TCA4311
boost current and the bus resistor and the equivalent capacitance on the line. If the pullup currents are the same,
a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two
sides. This effect is displayed in Figure 1 for VCC = 3.3 V and a 10-kΩ pullup resistor on each side (50 pF on one
side and 150 pF on the other). Since the output side has less capacitance than the input, it rises faster and the
effective tPLH is negative.
There is a finite propagation delay, tPHL, through the connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same VCC, pullup resistors and equivalent capacitance conditions as used in
Figure 1. An external NMOS device pulls down the voltage on the side with 150 pF capacitance; the TCA4311
pulls down the voltage on the opposite side, with a delay of 55 ns. This delay is always positive and is a function
of supply voltage, temperature and the pullup resistors and equivalent bus capacitances on both sides of the
bus. The Typical Performance Characteristics section shows tPHL as a function of temperature and voltage for
6
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