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CDCE18005 Fiches technique(PDF) 1 Page - Texas Instruments

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No de pièce CDCE18005
Description  Five/Ten Output Clock Generator/Buffer
Download  58 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

CDCE18005 Fiches technique(HTML) 1 Page - Texas Instruments

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1
FEATURES
APPLICATIONS
DESCRIPTION
LVPECL 1.5GHz/LVDS800MHz
CDCE18005
Crystal 25MHz
LVPECL 1.5GHz
LVDS 800MHz
LVDS 750MHz
LVPECL 800MHz
LVCMOS 25MHz
LVCMOS 25MHz
CDCE18005
www.ti.com........................................................................................................................................................................................... SCAS863 – NOVEMBER 2008
Five/Ten Output Clock Generator/Buffer
• Data Converter and Data Aggregation Clocking
• Universal Input Buffers That Accept LVPECL,
LVDS, or LVCMOS Level Signaling
• Wireless Infrastructure
• Switches and Routers
• Fully Configurable Outputs Including
Frequency, Output Format, and Output Skew
• Medical Electronics
• Military and Aerospace
• Output Multiplexer That Serves as a Clock
Switch Between the Three Reference Inputs
• Industrial
and the Outputs
• Clock Fan-out
• Clock Generation Via AT-Cut Crystal
• Integrated EEPROM Determines Device
Configuration at Power-up
The
CDCE18005
is
a
high
performance
clock
generator and distributor featuring a high degree of
• Low Additive Jitter Performance
configurability via a SPI interface, and programmable
• Universal Output Blocks Support up to 5
start up modes determined by on-board EEPROM.
Differential, 10 Single-ended, or Combinations
Specifically tailored for buffering clocks for data
of Differential or Single-ended:
converters
and
high-speed
digital
signals,
the
Low Additive Jitter
CDCE18005 achieves low additive jitter in the 50 fs
RMS(1) range. The clock distribution block includes
Output Frequency up to 1.5 GHz
five individually programmable outputs that can be
LVPECL, LVDS, LVCMOS, and Special High
configured to provide different combinations of output
Output Swing Modes
formats (LVPECL, LVDS, LVCMOS). Each output can
Independent Output Dividers Support
also be programmed to a unique output frequency
Divide Ratios from 1–80
(up to 1.5 GHz(2) ) and skew relationship via a
programmable
delay
block.
If
all
outputs
are
Independent limited Coarse Skew Control
configured in single-ended mode (e.g. LVCMOS), the
on all Outputs
CDCE18005 supports up to ten outputs. Each output
• Flexible Inputs:
can select one of three clock input sources. The input
Two Universal Differential Inputs Accept
block includes two universal differential inputs which
support frequencies up to 1500 MHz and an auxiliary
Frequencies up to 1500 MHz (LVPECL), 800
single ended input that can be connected to a CMOS
MHz (LVDS), or 250 MHz (LVCMOS).
level clock or configured to connect to an external
One Auxiliary Input Accepts Single Ended
crystal via an on board oscillator block.
Clock Source or Crystal. Auxiliary Input
Accepts Crystals in the Range of 2 MHz–42
MHz or an LVCMOS Input up to 75 MHz.
Clock Generator Mode Using Crystal Input.
• Typical Power Consumption 1.0W at 3.3V (see
Table 27)
• Integrated EEPROM Stores Default Settings;
Therefore, The Device Powers up in a Known,
Predefined State.
• Offered in QFN-48 Package
Figure 1. CDCE18005 Application Example
• ESD Protection Exceeds 2kV HBM
• Industrial Temperature Range –40°C to 85°C
(1)
12 kHz to 20 MHz integration bandwidth.
(2)
Maximum output frequency depends on the output format
selected
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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