Moteur de recherche de fiches techniques de composants électroniques |
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ML2724 Fiches technique(PDF) 10 Page - Micro Linear Corporation |
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ML2724 Fiches technique(HTML) 10 Page - Micro Linear Corporation |
10 / 26 page ML2724 DS2724-F-03 FINAL DATASHEET DECEMBER 2005 10 MODE CONTROL AND INTERFACE LINES 1 XCEN I (CMOS) Enables the bandgap reference and voltage regulators when high. Consumes only leakage current in STANDBY mode when low. This is a CMOS input, and the thresholds are referenced to VDD and VSS. 2 RXON I (CMOS) TX/RX Control Input. Switches the transceiver between TRANSMIT and RECEIVE modes. Circuits are powered up and signal paths reconfigured according to the operating mode. This is a CMOS input, and the thresholds are referenced to VDD and VSS. 1 VSS XCEN VDD RXON DIN 2 30 31 8 3 PAON O (CMOS) PA Control Output. Enables the off-chip PA at the correct times in a Transmit slot. Goes high when transmit RF is present at TXO; goes low 5μs before transmit RF is removed from TXO. Has interlock logic to shut down the PA if the PLL does not lock. 31 VSS VDD 3 PAON 8 9 FREF I Input for the 12.288MHz or 6.144MHz reference frequency. This input is used as the reference frequency for the PLL and as a calibration frequency for the on- chip filters. An AC-coupled sine or square wave source drives this self- biased input. 9 VSS FREF VCCA 24 8 40k 40k 11 QPO O Charge Pump Output of the phase detector. This is connected to the external PLL loop filter. 10 VSS RVPLL 11 QPO 8 |
Numéro de pièce similaire - ML2724 |
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Description similaire - ML2724 |
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