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CS42325 Fiches technique(PDF) 30 Page - Cirrus Logic |
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CS42325 Fiches technique(HTML) 30 Page - Cirrus Logic |
30 / 71 page 30 DS838A2 CS42325 4.2.1 Master Mode As a clock master, the LRCKx and SCLKx of each serial port will operate as outputs. The two serial ports may be independently placed into Master or Slave Mode. Each LRCKx and SCLKx are internally derived from the MCLKx selected by the SP1_MCLK and SP2_MCLK signals as shown in Figure 10. 4.2.2 Slave Mode In Slave Mode, SCLKx and LRCKx operate as inputs. Each serial port may be independently placed into Slave Mode. The Left/Right clock signal, LRCKx, must be equal to the sample rate, Fs. The serial bit clock, SCLKx, must be equal to 128x, 64x, 48x, or 32x Fs depending on the desired speed mode. Refer to Table 6 for required serial bit clock to Left/Right clock ratios. If operating in Asynchronous Mode, LRCK1 and SCLK1 must be synchronously derived from the SP1’s selected MCLK, and LRCK2 and SCLK2 must be synchronously derived from SP2’s selected MCLK. If operating in Synchronous Mode, SCLK1, LRCK1, SCLK2 and LRCK2 must be synchronously derived from the same MCLK. For more information on Synchronous and Asynchronous Modes, see “Synchro- nous / Asynchronous Mode” on page 29. The speed of each serial port is automatically determined based on the input MCLKx to LRCKx ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLKx using either the MCLKx FREQ bits or the MDIV hardware control pin. Serial Data Format SCLKx to LRCKx Ratio Single Speed Mode Double Speed Mode I²S, LJ or RJ Data Format 32, 48, 64, 128 32, 48, 64 Table 6. Slave Mode SCLK/LRCK Ratios Mode MCLKx to LRCKx Ratio Single Speed Mode Double Speed Mode SW Auto Mode Detect 256, 384, 512, 768 128, 192, 256, 384 HW Auto Mode Detect 256, 512 128, 256 See Table 3 an Table 4 on page 28 for clock ratio configuration. Table 7. MCLKx to LRCKx Ratios ÷256 ÷128 ÷4 ÷2 0 1 Generated-LRCK1 Generated-SCLK1 00 01 10 ÷1 ÷1.5 ÷2 11 ÷3 MCLK1 ÷256 ÷128 ÷4 ÷2 Generated-LRCK2 Generated-SCLK2 0 1 SP2_SPEED SP1_SPEED SP2_MCLK MCLK1 FREQ[1:0] 0 1 0 1 0 1 00 01 10 ÷1 ÷1.5 ÷2 11 ÷3 MCLK2 MCLK2 FREQ[1:0] 0 1 SP1_MCLK Internal-MCLK1 Internal-MCLK2 Figure 10. Master Mode Clock Generation |
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