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CS42325 Fiches technique(PDF) 59 Page - Cirrus Logic |
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CS42325 Fiches technique(HTML) 59 Page - Cirrus Logic |
59 / 71 page DS838A2 59 CS42325 6.17 DAC2x Volume Control: DAC1A (Address 14h) & DAC1B (Address 15h) The level for each channel of DAC2 output can be adjusted in 0.5 dB increments as dictated by the DAC2 Soft and Zero Cross bits (DAC2_SOFT & DAC2_ZC) from 0 to -127.5 dB. Levels are decoded in unsigned, as shown in the table below. 6.18 Interrupt Mode (Address 16h) The Interrupt Mode register contains four two-bit codes which correspond to either an Interrupt Status bit or group of bits as shown below. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising-edge Active Mode, the INT pin becomes active on the arrival of the interrupt condi- tion. In the Falling-edge Active Mode, the INT pin becomes active on the removal of the interrupt condition. In Level Active Mode, the INT pin remains active during the interrupt condition . 6.19 Interrupt Mask (Address 17h) These bits are mask bits for the corresponding bits in the “Interrupt Status (Address 18h) (Read Only)” reg- ister on page 61. 7 6 5 432 10 DAC2x_VOL7 DAC2x_VOL6 DAC2x_VOL5 DAC2x_VOL4 DAC2x_VOL3 DAC2x_VOL2 DAC2x_VOL1 DAC2x_VOL0 Binary Code Volume Setting 0000 0000 0 dB 0000 0001 -0.5 dB 0000 0010 -1.0 dB ··· ··· 1111 1111 -127.5 dB 7 6 5 432 10 SP2_ CLKERR1 SP2_ CLKERR0 SP1_ CLKERR1 SP1_ CLKERR0 DAC_AMUTE1 DAC_AMUTE0 ADC_ OVFLx1 ADC_ OVFLx0 Interrupt Mode Associated Interrupt Status Bit(s) SP2_CLKERR[1:0] SP2_CLKERR SP1_CLKERR[1:0] SP1_CLKERR DAC_AMUTE[1:0] DAC2_AMUTEL, DAC2_AMUTER, DAC1_AMUTEL, DAC1_AMUTER ADC_AVFLx[1:0] ADC_OVFLP, ADC_OVFLN Bit Settings Interrupt Mode Setting 00 Rising-edge Active 01 Falling-edge Active 10 Level Active 11 Reserved 7 6 5 432 10 DAC2_ AMUTELM DAC2_ AMUTERM DAC1_ AMUTELM DAC1_ AMUTERM SP2_ CLKERRM SP1_ CLKERRM ADC_ OVFLPM ADC_ OVFLNM Bit Settings Bit in Interrupt Register 0 Not Masked 1 Masked |
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