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CS4265 Fiches technique(PDF) 23 Page - Cirrus Logic |
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CS4265 Fiches technique(HTML) 23 Page - Cirrus Logic |
23 / 56 page DS657F2 23 CS4265 3. TYPICAL CONNECTION DIAGRAM VLS 10 µF +3.3V to +5V 47 µF VQ FILT+ 0.1 µF 10 µF 0.1 µF 10 µF 0.1 µF +1.8V to +5V DGND VLC 0.1 µF +1.8V to +5V SCL SDA RST 2 k Ω Note 1 LRCK SDIN1 AGND Digital Audio Processor Micro- Controller MCLK SCLK 0.1 µF VA VD * Capacitors must be C0G or equivalent Digital Audio Output 2.2nF AFILTA AFILTB MICIN1 MICIN2 Microphone Input 1 Microphone Input 2 2.2nF SDIN2 TXOUT TXSDIN SDOUT CS4265 2 k Ω 0.1 µF 10 µF MICBIAS ** +3.3V to +5V SGND Signal Ground MUTEC Mute Drive AOUTA AOUTB 470 Ω 470 Ω 3.3 µF C Optional Analog Muting 3.3 µF 10 k Ω 10 k Ω C Rext Rext See Note 2 * * AIN1A Left Analog Input 1 10 µF 10 µF 1800 pF 1800 pF 100 k Ω 100 k Ω 100 Ω 100 Ω AIN1B Right Analog Input 1 * * 10 µF 10 µF 10 µF Note 1: Resistors are required for I²C control port operation For best response to Fs/2 : () 470 4 470 × + = ext ext R Fs R C π This circuitry is intended for applications where the CS4265 connects directly to an unbalanced output of the design . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. Note 2 : RL RL Note 3 Note 3: The value of RL is dictated by the microphone carteridge. VA 0.1 µF AGND 47 k Ω Note 4: Sets the LSB of the 7-bit chip address. See the I²C Control Port Description and Timing section. Note 4 Figure 9. Typical Connection Diagram |
Numéro de pièce similaire - CS4265_07 |
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Description similaire - CS4265_07 |
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