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FDS6690AS Fiches technique(PDF) 6 Page - Texas Instruments |
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FDS6690AS Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 33 page DEVICE INFORMATION TPS51123 SLUS890 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Table 1. TERMINAL FUNCTIONS TABLE TERMINAL I/O DESCRIPTION NAME NO. DRVH1 21 O High-side N-channel MOSFET driver outputs. LL referenced drivers. DRVH2 10 DRVL1 19 O Low-side N-channel MOSFET driver outputs. GND referenced drivers. DRVL2 12 Master enable input. EN0 13 I/O Open : LDOs on, and ready to turn both switcher channels. GND : disable all circuit Channel 1 and Channel 2 enable input. Pull up to the voltage ranging 3.3-V to 5-V to turn on both ENC 18 I switcher channels. Short to ground to shutdown them. GND 15 – Ground. LL1 20 I Switch node connections for high-side drivers, current limit and control circuitry. LL2 11 PGOOD 23 O Powergood window comparator output for channel 1 and 2. (Logical AND) Selection pin for operation mode: OOA auto skip : Connect to VREG3 or VREG5 SKIPSEL 14 I PWM only: Connect to VREF Auto skip: Connect to GND TRIP1 1 I/O OCL trip setting pins. Connect resistor from this pin to GND to set threshold for synchronous RDS(on) sense. TRIP2 6 On-time adjustment pin. 365 kHz/460 kHz setting: connect to VREG5 TONSEL 4 I 300 kHz/375 kHz setting: connect to VREG3 245 kHz/305 kHz setting: connect to VREF 200 kHz/250 kHz setting: connect to GND VBST1 22 I Supply input for high-side N-channel MOSFET driver (boost terminal). VBST2 9 VFB1 2 I SMPS feedback inputs. Connect with feedback resistor divider. VFB2 5 VIN 16 I High voltage power supply input for 5-V/3.3-V LDO. VO1 24 Output connection to SMPS. These terminals work as fixed voltage inputs and output discharge I/O inputs. VO1 and VO2 also work as 5-V and 3.3-V switch over return power input respectively. VO2 7 2-V reference voltage output. Connect 220-nF to 1- µF ceramic capacitor to Signal GND near the VREF 3 O device. 3.3-V power supply output. Connect a 10- µF ceramic capacitor to Power GND near the device. A VREG3 8 O 1- µF ceramic capacitor is acceptable when not loaded. VREG5 17 O 5-V power supply output. Connect a 33- µF ceramic capacitor to Power GND near the device. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS51123 |
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