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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPS54617RUV Fiches technique(PDF) 9 Page - Texas Instruments |
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TPS54617RUV Fiches technique(HTML) 9 Page - Texas Instruments |
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9 / 18 page  FEEDBACK CIRCUIT OPERATING FREQUENCY ( ) 51000 4400 = + SW T F R (1) OUTPUT FILTER PCB LAYOUT TPS54617 www.ti.com ........................................................................................................................................................................................... SLVS880 – NOVEMBER 2008 cause problems with some of the control and bias signals. For these reasons, separate analog and The values for these components are selected to power ground traces are recommended. There provide fast transient response times. should be an area of ground on the top layer directly under the IC, with an exposed area for connection to The resistor divider network of R1 and R2 sets the the PowerPAD. Use vias to connect this ground area output voltage for the circuit at 1.8 V. R1 along with to any internal ground planes. Use additional vias at R6, R7, C5, C7, and C10 forms the loop the ground side of the input and output filter compensation network for the circuit. For this design, capacitors as well. The AGND and PGND pins should a Type-3 topology is used. The feedback loop is be tied to the PCB ground by connecting them to the compensated so that the closed loop crossover ground area under the device as shown. Use a frequency is approximately 45 kHz at 5 V input. separate wide traces for the analog ground signal path. This analog ground should be used for the voltage set point divider, timing resistor RT, slow start In the application circuit, RT is grounded through a capacitor, and bias capacitor grounds. Connect this 27.4-k Ω resistor to select the operating frequency of trace the topside groud area near AGND (Pin 1). 1.6 MHz. To set a different frequency, place a 27-k Ω The PH pins should be tied together and routed to to 180-k Ω resistor between RT (pin 29) and analog the output inductor. Since the PH connection is the ground or leave RT floating to select the default of switching node, the inductor should be located very 350 kHz. The switching frequency in MHz can be close to the PH pins and the area of the PCB approximated using the following equation: conductor minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The output filter is composed of a 0.82-µH inductor and 2 × 100-µF capacitors. The inductor is a Vishay Connect the output filter capacitor(s) as shown IHLM-2525CZ-01 type. The capacitors used are between the VOUT trace and PGND. It is important to 100-µF, 6.3-V ceramic types with X5R dielectric. keep the loop formed by the PH pins, Lout, Cout and PGND as small as practical. Place the compensation components from the VOUT Figure 11 shows a generalized PCB layout guide for trace to the VSENSE and COMP pins. Do not place the TPS54617. The VIN pins should be connected these components too close to the PH trace. Due to together on the printed circuit board (PCB) and the size of the IC package and the device pinout, the bypassed with a low ESR ceramic bypass capacitor. components will have to be routed somewhat close, Care should be taken to minimize the loop area but maintain as much separation as possible while formed by the bypass capacitor connections, the VIN still keeping the layout compact. pins, and the TPS54617 ground pins. The minimum Connect the bias capacitor from the VBIAS pin to recommended bypass capacitance is 10 µF ceramic analog ground using the isolated analog ground with a X5R or X7R dielectric and the optimum trace. If a slow-start capacitor or RT resistor is used, placement is closest to the VIN pins and the PGND or if the SYNC pin is used to select 350 kHz pins. operating frequency, connect them to this trace as The TPS54617 has two internal grounds (analog and well. power). The analog ground ties to all of the noise-sensitive signals, while the power ground ties to the noisier power signals. Noise injected between the two grounds can degrade the performance of the TPS54617, particularly at higher output currents. Ground noise on an analog ground plane can also Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :TPS54617 |
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Description similaire - TPS54617RUV |
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