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AD5025 Datasheet(Fiches technique) 5 Page - Analog Devices

Numéro de pièce AD5025
Description  Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
Télécharger  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5025 Datasheet(HTML) 5 Page - Analog Devices

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AD5025/AD5045/AD5065
Rev. 0 | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SCLK Cycle Time
t11
20
ns
SCLK High Time
t2
10
ns
SCLK Low Time
t3
10
ns
SYNC to SCLK Falling Edge Setup Time
t4
16.5
ns
Data Setup Time
t5
5
ns
Data Hold Time
t6
5
ns
SCLK Falling Edge to SYNC Rising Edge
t7
0
30
ns
Minimum SYNC High Time (Single Channel Update)
t8
2
μs
Minimum SYNC High Time (All Channel Update)
t8
4
μs
SYNC Rising Edge to SCLK Fall Ignore
t9
17
ns
LDAC Pulse Width Low
t10
20
ns
SCLK Falling Edge to LDAC Rising Edge
t11
20
ns
CLR Pulse Width Low
t12
10
ns
SCLK Falling Edge to LDAC Falling Edge
t13
10
ns
CLR Pulse Activation Time
t14
10.6
μs
SCLK Rising Edge to SDO Valid
t152, 3
22
ns
SCLK Falling Edge to SYNC Rising Edge
t162
5
30
ns
SYNC Rising Edge to SCLK Rising Edge
t172
8
ns
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)
t182
2
μs
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)
t182
4
μs
PDL Minimum Pulse Width
t19
20
ns
1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2 Daisy-chain mode only.
3 Measured with the load circuit of Figure 2. t15 determines the maximum SCLK frequency in daisy-chain mode.
Circuit and Timing Diagrams
2mA
IOL
2mA
IOH
VOH (MIN) + VOL (MAX)
2
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications


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