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AD5100 Fiches technique(PDF) 7 Page - Analog Devices |
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AD5100 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 36 page AD5100 Rev. 0 | Page 7 of 36 TIMING SPECIFICATIONS Table 3. Parameter Description Min Typ Max Unit I2C INTERFACE TIMING CHARACTERISTICS1, 2 fSCL SCL clock frequency 400 kHz t1 tBUF, bus free time between start and stop 1.3 μs t2 tHD;STA, hold time after (repeated) start condition; after this period, the first clock is generated 0.6 μs t3 tLOW, low period of SCL clock 1.3 μs t4 tHIGH, high period of SCL clock 0.6 50 μs t5 tSU;STA, setup time for start condition 0.6 μs t6 tHD;DAT, data hold time 0.9 μs t7 tSU;DAT, data setup time 0.1 μs t8 tF, fall time of both SDA and SCL signals 0.3 μs t9 tR, rise time of both SDA and SCL signals 0.3 μs t10 tSU;STO, setup time for stop condition 0.6 μs 1 Guaranteed by design and not subject to production test. 2 See Figure 2. SCL t2 t3 t4 t7 t5 t10 t2 t8 t1 PS SP t9 t6 t8 SDA t9 Figure 2. Digital Interface Timing Diagram |
Numéro de pièce similaire - AD5100_08 |
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Description similaire - AD5100_08 |
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