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CD-700-LAF-NBC-77.760 Datasheet(Fiches technique) 2 Page - Vectron International, Inc

Numéro de pièce CD-700-LAF-NBC-77.760
Description  Complete VCXO Based Phase Lock Loop
Télécharger  14 Pages
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Fabricant  VECTRON [Vectron International, Inc]
Site Internet  http://www.vectron.com
Logo VECTRON - Vectron International, Inc

CD-700-LAF-NBC-77.760 Datasheet(HTML) 2 Page - Vectron International, Inc

  CD-700-LAF-NBC-77.760 Datenblatt HTML 1Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datasheet HTML 2Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datenblatt HTML 3Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datenblatt HTML 4Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datenblatt HTML 5Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datenblatt HTML 6Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datenblatt HTML 7Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datenblatt HTML 8Page - Vectron International, Inc CD-700-LAF-NBC-77.760 Datenblatt HTML 9Page - Vectron International, Inc Next Button
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CD-700, VCXO Based PLL
Vectron International 166 Glover Avenue, Norwalk CT 06856-5160
Tel:1-88-VECTRON-1
e-mail: vectron@vectron.com
Performance Characteristics
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
Output Frequency (ordering option)
OUT1, 5.0 V option
OUT1, 3.3 V option
1.000
1.000
77.760
77.760
MHz
MHz
Supply Voltage
1
+5.0
+3.3
VDD
4.5
2.97
5.0
3.3
5.5
3.63
V
V
Supply Current
IDD
63
mA
Output Logic Levels
Output Logic High
2
Output Logic Low
2
VOH
VOL
2.5
0.5
V
V
Output Transition Times
Rise Time
2
Fall Time
2
tR
tF
5
5
ns
ns
Input Logic Levels
Output Logic High
2
Output Logic Low
2
VIH
VIL
2.0
0.5
V
V
Loss of Signal Indication
Output Logic High
2
Output Logic Low
2
VOH
VOL
2.5
0.5
V
V
Nominal Frequency on Loss of Signal
Output 1
Output 2
±75
±75
ppm
ppm
Symmetry or Duty Cycle
3
Out 1
Out 2
RCLK
SYM1
SYM2
RCLK
40/60
45/55
40/60
%
%
%
Absolute Pull Range (ordering option)
over operating temperature, aging, and
power supply variations
APR
±50
±80
±100
ppm
Test Conditions for APR (+5.0 V option)
VC
0.5
4.5
V
Test Conditions for APR (+3.3 V option)
VC
0.3
3.0
V
Gain Transfer
Positive
Phase Detector Gain
+5V option
+3.3V option
0.53
0.35
rad/V
rad/V
Operating temperature (ordering option)
0/70 or –40/85
°C
Control Voltage Leakage Current
IVCXO
±1
uA
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which
these parameters are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RCLK, RDATA
80
%
1.4V
20
%
tF
tR
Period
On Time
+
-
+
-
IC
VC
13
.1μF
.01
μF
15pF
14
16
IDD
650
Ω
VDD
1.8k
7


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