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MCZ33972AEWR2 Fiches technique(PDF) 8 Page - Freescale Semiconductor, Inc

No de pièce MCZ33972AEWR2
Description  Multiple Switch Detection Interface with Suppressed Wake-Up
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCZ33972AEWR2 Fiches technique(HTML) 8 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
8
Freescale Semiconductor
33972
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1V
≤ V
DD ≤ 5.25V, 8.0V ≤ VPWR ≤ 16V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
tPULSE(ON)
15
16
20
ms
Interrupt Delay Time
Normal Mode
tINT-DLY
5.0
16
μs
Sleep Mode Switch Scan Time
tSCAN
100
200
300
μs
Calibrated Scan Timer Accuracy
Sleep Mode
tSCAN TIMER
10
%
Calibrated Interrupt Timer Accuracy
Sleep Mode
tINT TIMER
10
%
DIGITAL INTERFACE TIMING(13)
Required Low-state Duration on VPWR for Reset
(14)
VPWR ≤ 0.2 V
tRESET
10
μs
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
tLEAD
100
ns
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
tLAG
50
ns
SI to Falling Edge of SCLK
Required Setup Time
tSI(SU)
16
ns
Falling Edge of SCLK to SI
Required Hold Time
tSI(HOLD)
20
ns
SI, CS, SCLK Signal Rise Time(15)
tR(SI)
5.0
ns
SI, CS, SCLK Signal Fall Time(15)
tF(SI)
5.0
ns
Time from Falling Edge of CS to SO Low-impedance(16)
tSO(EN)
55
ns
Time from Rising Edge of CS to SO High-impedance(17)
tSO(DIS)
55
ns
Time from Rising Edge of SCLK to SO Data Valid(18)
tVALID
25
55
ns
Notes
13.
These parameters are guaranteed by design. Production test equipment uses 4.16MHz, 5.0V SPI interface.
14.
This parameter is guaranteed by design but not production tested.
15.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16.
Time required for valid output status data to be available on SO pin.
17.
Time required for output states data to be terminated at SO pin.
18.
Time required to obtain valid data out from SO following the rise of SCLK with 200pF load.


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