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AD7190 Fiches technique(PDF) 1 Page - Analog Devices |
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AD7190 Fiches technique(HTML) 1 Page - Analog Devices |
1 / 21 page 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA Preliminary Technical Data AD7190 Rev.PrD 7/08 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2008 Analog Devices, Inc. All rights reserved. FEATURES RMS Noise: 7 nV @ 4.7 Hz (gain = 128) 16.5 noise free bits @ 2.4 kHz (gain = 128) Up to 23 noise free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 2 ppm/°C Specified drift over time Programmable gain (1 – 128) Update rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection Four general purpose digital outputs Power supply: 3 V to 5.25 V Current: 6 mA Temperature range: –40°C to +105°C INTERFACE 3-wire serial SPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Strain gauge transducers Pressure measurement Temperature measurement Chromatography PLC/DCS Analog Input Modules Data Acquisition Medical and Scientific instrumentation GENERAL DESCRIPTION The AD7190 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24- bit ∑-∆ ADC. The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The device can be configured to have two differential inputs or four pseudo-differential inputs. The device can be operated with either the internal clock or an external clock. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz. The device can be operated with a sinc3 or a sinc4 digital filter. At the lower update rates, the sinc3 is useful to optimize the settling time. The benefit of the sinc4 at low update rates is the superior 50 Hz/60 Hz rejection. At the higher update rates, the sinc4 filter gives best noise performance. For applications that require all conversions to be settled, the AD7190 includes a zero-latency feature. The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 6 mA. It is housed in a 24-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM AIN1 AIN2 MUX AVDD AGND AIN3 AIN4 AD7190 SERIAL INTERFACE AND CONTROL LOGIC MCLK1 SIGMA DELTA ADC PGA REFIN1(+) REFIN1(-) REFERENCE DETECT AGND AVDD DOUT/RDY DIN SCLK CS CLOCK CIRCUITRY MCLK2 AINCOM DGND DVDD SYNC P0/REFIN2(-) P1/REFIN2(+) P2 P3 TEMP SENSOR BPDSW AGND Figure 1. |
Numéro de pièce similaire - AD7190 |
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Description similaire - AD7190 |
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