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ADE7761BARSZ Fiches technique(PDF) 4 Page - Analog Devices |
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ADE7761BARSZ Fiches technique(HTML) 4 Page - Analog Devices |
4 / 24 page ADE7761B Rev. 0 | Page 4 of 24 Parameter Value Unit Test Conditions/Comments LOGIC INPUTS5 PGA, SCF, S1, and S0 Input High Voltage, VINH 2.4 V, min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 V, max VDD = 5 V ± 5% Input Current, IIN ±3 μA, max Typical 10 nA, VIN = 0 V to VDD Input Capacitance, CIN 10 pF, max LOGIC OUTPUTS5 CF, REVP, and FAULT Output High Voltage, VOH 4 V, min VDD = 5 V ± 5% Output Low Voltage, VOH 1 V, max VDD = 5 V ± 5% F1 and F2 Output High Voltage, VOH 4 V, min VDD = 5 V ± 5%, ISOURCE = 10 mA Output Low Voltage, VOH 1 V, max VDD = 5 V ± 5%, ISINK = 10 mA POWER SUPPLY For specified performance VDD 4.75 V, min 5 V − 5% 5.25 V, max 5 V + 5% IDD 3.65 mA, max 1 See plots in the Typical Performance Characteristics section. 2 See the Terminology section for explanation of specifications. 3 See the Fault Detection section for explanation of fault detection functionality. 4 See the Missing Neutral Detection section for explanation of missing neutral detection functionality. 5 Sample tested during initial release and after any redesign or process change that might affect this parameter. TIMING CHARACTERISTICS VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, TMIN to TMAX = −40°C to +85°C. Sample tested during initial release and after any redesign or process change that might affect this parameter. See Figure 2. Table 2. Parameter Value Unit Test Conditions/Comments t11 120 ms F1 and F2 pulse width (logic high) t2 See Table 8 sec Output pulse period (see the Transfer Function section) t3 1/2 t2 sec Time between F1 falling edge and F2 falling edge t41 90 ms CF pulse width (logic high) t5 See Table 8 sec CF pulse period (see the Transfer Function section) t6 CLKIN/4 sec Minimum time between F1 pulse and F2 pulse 1 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section. Timing Diagram t1 t6 t3 t4 t2 t5 F1 F2 CF Figure 2. Timing Diagram for Frequency Outputs |
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