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ST92250V2TB Fiches technique(PDF) 45 Page - STMicroelectronics |
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ST92250V2TB Fiches technique(HTML) 45 Page - STMicroelectronics |
45 / 426 page 45/426 ST92F124/F150/F250 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. Bits 7:0 = DPR0_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh. DATA PAGE REGISTER 1 (DPR1) R241 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R225 if EMR2.5 is set. Bits 7:0 = DPR1_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh. DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2.5 is set. Bits 7:0 = DPR2_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh. DATA PAGE REGISTER 3 (DPR3) R243 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R227 if EMR2.5 is set. Bits 7:0 = DPR3_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh. 70 DPR0 _7 DPR0 _6 DPR0 _5 DPR0 _4 DPR0 _3 DPR0 _2 DPR0 _1 DPR0 _0 70 DPR1 _7 DPR1 _6 DPR1 _5 DPR1 _4 DPR1 _3 DPR1 _2 DPR1 _1 DPR1 _0 70 DPR2 _7 DPR2 _6 DPR2 _5 DPR2 _4 DPR2 _3 DPR2 _2 DPR2 _1 DPR2 _0 70 DPR3 _7 DPR3 _6 DPR3 _5 DPR3 _4 DPR3 _3 DPR3 _2 DPR3 _1 DPR3 _0 9 |
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