Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼

Delete All


Preview PDF Download HTML

LC4064ZE4MN48CES Datasheet(Fiches technique) 7 Page - Lattice Semiconductor

Numéro de pièce LC4064ZE4MN48CES
Description  1.8V In-System Programmable Ultra Low Power PLDs
Télécharger  54 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  LATTICE [Lattice Semiconductor]
Site Internet
Logo LATTICE - Lattice Semiconductor

LC4064ZE4MN48CES Datasheet(HTML) 7 Page - Lattice Semiconductor

Back Button LC4064ZE4MN48CES Datenblatt HTML 3Page - Lattice Semiconductor LC4064ZE4MN48CES Datenblatt HTML 4Page - Lattice Semiconductor LC4064ZE4MN48CES Datenblatt HTML 5Page - Lattice Semiconductor LC4064ZE4MN48CES Datenblatt HTML 6Page - Lattice Semiconductor LC4064ZE4MN48CES Datasheet HTML 7Page - Lattice Semiconductor LC4064ZE4MN48CES Datenblatt HTML 8Page - Lattice Semiconductor LC4064ZE4MN48CES Datenblatt HTML 9Page - Lattice Semiconductor LC4064ZE4MN48CES Datenblatt HTML 10Page - Lattice Semiconductor LC4064ZE4MN48CES Datenblatt HTML 11Page - Lattice Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 54 page
background image
Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
• Block CLK2
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
Initialization Control
The ispMACH 4000ZE family architecture accommodates both block-level and macrocell-level set and reset capa-
bility. There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macro-
cell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset
functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, pro-
viding flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset
delay time has elapsed.
GLB Clock Generator
Each ispMACH 4000ZE device has up to four clock pins that are also routed to the GRP to be used as inputs.
These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock sig-
nals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations
of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
Block CLK0
Block CLK1
Block CLK2
Block CLK3

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54 

Datasheet Download

Go To PDF Page

Lien URL

Privacy Policy
AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicit   |   Contactez-nous   |   Politique de confidentialit   |   Echange de liens   |   Manufacturer List
All Rights Reserved©

Mirror Sites
English :  |   English :  |   Chinese :  |   German :  |   Japanese :
Russian :  |   Korean :  |   Spanish :  |   French :  |   Italian :
Portuguese :  |   Polish :  |   Vietnamese :