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STLC5460 Fiches technique(PDF) 5 Page - STMicroelectronics |
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STLC5460 Fiches technique(HTML) 5 Page - STMicroelectronics |
5 / 54 page LINE CARD APPLICATIONS The LCIC is designed to fit both digital and ana- logue line card architectures. It supports up to 16 ISDN subscribers or 16 voice subscribers. The level 1 devices are connected to ST5451 circuits to perform the D channel han- dling. Analogue Line Card In analogue line cards LCIC controls signalling, voice and data path of 64 kb/s channels. When used in combination with L3040/L300 0N, it allows to implement an optimised line card archi- tecture: the LCIC controls the configuration of L3040 and exchange signalling with the L3040. Digital Line Card In digital line cards LCIC controls the configura- tion of Level 1 circuits (U or S Interface) by means of MON channel configuration and per- forms activation/deactivation by means of Com- mand/Indicate protocol. LCIC switches the B channels and can switch the D channels if the processing is centralised. FUNCTIONAL DESCRIPTION PCM INTERFACE The PCM Interface Registers configure the data transmitted or received at the PCM port, for one PCM, the maximum data rate can change de- pending on the Mode selected: PCM Mode 0: max rate 2048 kb/s with four PCM ports active PCM Mode 1: max rate 4096 kb/s with two PCM ports active PCM Mode 2: max rate 8192 kb/s with one PCM ports active. The ”actual data” rate may be varied in a wide range without programming. An automate computes the number of clock per frame. Hence, the data rate can be stepped in 8, 16 or 32 kb/s in increments in PCM mode 0, 1, 2 respectively. The clock frequency of PDC is equal to once or twice the data rate, See fig 1 and 2. When operat- ing at single rate (2048 kb/s) and not at double clock frequency (4096 kHz), an onchip clock fre- quency doubler provides a 4098 kHz clock for the GCI interface (DCL). The rising edge of PFS signal is used to deter- mine the first bit of the first time slot of the frame. The length of PFS pulse is one bit-time at least and the length between two pulses can be also one bit time. After reset, the LCIC reaches synchronism having received two consecutive correct PFS pulses. Synchronisation is considered lost by the device if the PFS signal is not repeated with the correct repetition rate which has been stored by the cir- cuit at the beginning of synchronisation research. The LSYNC bit in the Interrupt Register indicates if the component is synchronised or not: a logical 0 indicates the synchronous state, a logical ”1” shows that the synchronism has been lost. The relation between the framing signal PFS and the bit stream is controlled by the contents of IPOF, OPOF and CPOF registers. These regis- ters denote the number of bit times the PCM frame is shifted. Each PCM multiplex can be pro- grammed with different shifts . Without programming the bit shift function of the PCM interface, the rising edge of the PFS signal marks the first bit of input PCM frame and the first bit of output PCM frame. See Fig 3 GCI Interface The Monitor and the Command/Indicate channels may be validated or not, in this second case the B3 and B4 channels become standard channels at 64 kb/s. When validated Command/Indicate channel may be configured with four bits for digital cards or six bits for analogue cards. The clocks (Bit clock and frame clock) are deliv- ered by the device with double rate clocking or simple rate clocking. FSC and DCL are output signals derived from PFS and PDC which are input signals. GCI PCM DCL clock kHz Data kb/s PDC Clock (kHz) Data rate kb/s Mode Simple (*) Double Simple Double 2.048 4.096 2.048 2.048 2.048 Mode 0 2.048 4.096 2.048 4.096 2.048 Mode 0 2.048 4.096 2.048 4.096 4.096 Mode 1 2.048 4.096 2.048 8.192 4.096 Mode 1 2.048 4.096 2.048 8.192 8.192 Mode 2 2.048 4.096 2.048 16.384 8.192 Mode 2 (*) as GCI format but with simple clock. STLC5460 5/54 |
Numéro de pièce similaire - STLC5460 |
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Description similaire - STLC5460 |
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