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STK3NA50 Fiches technique(PDF) 1 Page - STMicroelectronics |
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STK3NA50 Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 10 page STK3NA50 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR s TYPICAL RDS(on) = 2.4 Ω s ± 30V GATE TO SOURCE VOLTAGE RATING s 100% AVALANCHE TESTED s REPETITIVE AVALANCHE DATA AT 100 oC s LOW INTRINSIC CAPACITANCES s GATE GHARGE MINIMIZED s REDUCED THRESHOLD VOLTAGE SPREAD DESCRIPTION This series of POWER MOSFETS represents the most advanced high voltage technology. The op- timized cell layout coupled with a new proprietary edge termination concur to give the device low RDS(on) and gate charge, unequalled ruggedness and superior switching performance. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE INTERNAL SCHEMATIC DIAGRAM TYPE VDSS R DS(on) ID STK3NA50 500 V < 3 Ω 2.7 A 1 2 3 SOT-82 SOT-194 (option) November 1996 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Uni t VDS Drain-source Voltage (VGS = 0) 500 V VDG R Drain- gate Voltage (RGS =20 k Ω) 500 V VGS Gate-source Voltage ± 30 V ID Drain Current (cont inuous) at T c =25 oC2.7 A ID Drain Current (cont inuous) at T c =100 oC1.7 A IDM( •) Drain Current (pulsed) 10.8 A Ptot Total Dissipation at Tc =25 oC50 W Derating Factor 0.4 W/ oC Tstg St orage Temperat ure -65 to 150 oC Tj Max. Operat ing Junction Temperature 150 oC ( •) Pulse width limited by safe operating area 1 2 3 1/10 |
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