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TPS73618DBVRG4 Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS73618DBVRG4 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 26 page PIN CONFIGURATIONS TABISGND DCQPACKAGE SOT223 (TOPVIEW) 5 IN OUT GND NR/FB EN DBVPACKAGE SOT23 (TOPVIEW) IN GND EN 3 NR/FB OUT 1 2 5 4 IN N/C N/C EN 8 7 6 5 OUT N/C NR/FB GND 1 2 3 4 DRBPACKAGE 3mmx3mmSON (TOPVIEW) 4 3 6 2 1 TPS736xx www.ti.com .................................................................................................................................................. SBVS038R – SEPTEMBER 2003 – REVISED MAY 2008 PIN DESCRIPTIONS SOT23 SOT223 3x3 SON (DBV) (DCQ) (DRB) NAME PIN NO. PIN NO. PIN NO. DESCRIPTION IN 1 1 8 Input supply GND 2 3, 6 4, Pad Ground Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the EN 3 5 5 regulator into shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to IN if not used. Fixed voltage versions only—connecting an external capacitor to this pin bypasses NR 4 4 3 noise generated by the internal bandgap, reducing output noise to very low levels. Adjustable voltage version only—this is the input to the control loop error amplifier, FB 4 4 3 and is used to set the output voltage of the device. OUT 5 2 1 Output of the Regulator. There are no output capacitor requirements for stability. Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS736xx |
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