Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

AD5024BRUZ-REEL7 Fiches technique(PDF) 6 Page - Analog Devices

No de pièce AD5024BRUZ-REEL7
Description  Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5024BRUZ-REEL7 Fiches technique(HTML) 6 Page - Analog Devices

Back Button AD5024BRUZ-REEL7 Datasheet HTML 2Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 3Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 4Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 5Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 6Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 7Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 8Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 9Page - Analog Devices AD5024BRUZ-REEL7 Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 28 page
background image
AD5024/AD5044/AD5064
Rev. 0 | Page 6 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX;
Parameter1
VDD = 4.5 V to 5.5 V
Unit
Conditions/Comments
t1
20
ns min
SCLK cycle time
t2
10
ns min
SCLK high time
t3
10
ns min
SCLK low time
t4
16.5
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
1.9
μs min
Minimum SYNC high time (single channel update)
10.5
μs min
Minimum SYNC high time (all channel update)
t9
17
ns min
SYNC rising edge to SCLK fall ignore
t10
20
ns min
LDAC pulse width low
t11
20
ns min
SCLK falling edge to LDAC rising edge
t12
10
ns min
CLR pulse width low
t13
10
ns min
SCLK falling edge to LDAC falling edge
t14
10.6
μs min
CLR pulse activation time
1 Guaranteed by design and characterization; not production tested.
t4
t3
SCLK
SYNC
DIN
t1
t2
t5
t6
t7
t8
DB23
t9
t10
t11
LDAC1
LDAC2
t13
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
CLR
t12
t14
VOUT
DB0
Figure 2. Serial Write Operation


Numéro de pièce similaire - AD5024BRUZ-REEL7

FabricantNo de pièceFiches techniqueDescription
logo
Analog Devices
AD5024BRUZ-REEL7 AD-AD5024BRUZ-REEL7 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Rev. F
AD5024BRUZ-REEL7 AD-AD5024BRUZ-REEL7 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad,SPI Interface
More results

Description similaire - AD5024BRUZ-REEL7

FabricantNo de pièceFiches techniqueDescription
logo
Analog Devices
AD5064BRUZ-1 AD-AD5064BRUZ-1 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Rev. F
AD5064 AD-AD5064_15 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Rev. F
AD5024 AD-AD5024_15 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Rev. F
AD5044 AD-AD5044_15 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Rev. F
AD5025 AD-AD5025_15 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
REV. 0
AD5025 AD-AD5025_08 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
REV. 0
AD5065 AD-AD5065_15 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
REV. 0
AD5045 AD-AD5045_15 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
REV. 0
AD5066 AD-AD5066_15 Datasheet
617Kb / 24P
   Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
REV. A
AD5066BRUZ AD-AD5066BRUZ Datasheet
617Kb / 24P
   Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
REV. A
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com