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AD5024BRUZ-REEL7 Datasheet(Fiches technique) 6 Page - Analog Devices

Numéro de pièce AD5024BRUZ-REEL7
Description  Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Télécharger  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5024BRUZ-REEL7 Datasheet(HTML) 6 Page - Analog Devices

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AD5024/AD5044/AD5064
Rev. 0 | Page 6 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX;
Parameter1
VDD = 4.5 V to 5.5 V
Unit
Conditions/Comments
t1
20
ns min
SCLK cycle time
t2
10
ns min
SCLK high time
t3
10
ns min
SCLK low time
t4
16.5
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
1.9
μs min
Minimum SYNC high time (single channel update)
10.5
μs min
Minimum SYNC high time (all channel update)
t9
17
ns min
SYNC rising edge to SCLK fall ignore
t10
20
ns min
LDAC pulse width low
t11
20
ns min
SCLK falling edge to LDAC rising edge
t12
10
ns min
CLR pulse width low
t13
10
ns min
SCLK falling edge to LDAC falling edge
t14
10.6
μs min
CLR pulse activation time
1 Guaranteed by design and characterization; not production tested.
t4
t3
SCLK
SYNC
DIN
t1
t2
t5
t6
t7
t8
DB23
t9
t10
t11
LDAC1
LDAC2
t13
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
CLR
t12
t14
VOUT
DB0
Figure 2. Serial Write Operation


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