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AD1884AJCPZ-RL Fiches technique(PDF) 7 Page - Analog Devices |
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AD1884AJCPZ-RL Fiches technique(HTML) 7 Page - Analog Devices |
7 / 20 page AD1884A Rev. 0 | Page 7 of 20 | March 2008 HD AUDIO LINK SPECIFICATION High Definition Audio signals comply with the High Definition Audio Specification. Please refer to these specifications at: www.intel.com/standards/hdaudio. POWER-DOWN STATES POWER SUPPLY Analog (AVDD) 3.3 V ± 5% Power Supply Range Power Dissipation Supply Current 3.13 3.30 75.9 23 3.46 V mW mA Digital (DVDD) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 141.9 43 3.63 V mW mA Digital (DVCORE) 1.7 V Through 1.9 V ± 10% Power Supply Range Power Dissipation Supply Current 1.615 1.70 61 36 1.995 V mW mA Digital I/O (DVIO) 3.3 V ± 10% Power Supply Range Power Dissipation Supply Current 2.97 3.30 3.3 1 3.63 V mW mA Digital I/O (DVIO) 1.5 V ± 5.5% Power Supply Range Power Dissipation Supply Current 1.418 1.50 0.08 0.05 1.583 V mW mA Power Supply Rejection (Reference to fS 100 mV p-p Signal @ 1 kHz) 1 80 dB 1 Guaranteed but not tested. Parameter Min Typ Max Unit Parameter IDVDD Typ (1.7 V) IDVDD Typ (3.3 V) IAVDD Typ Unit Function Node in D0, All Nodes Active 36 43 23 mA Function Node in D3 15.75 17 1 mA Function Node in D3 1 1 Maximum power saving mode; Register 0x31FD, Bit 4. 7.5 7.5 1 mA Codec in RESET 33 3mA Individual Block Power Savings DAC Pair Powered Down Saves (Each) ADC Pair Powered Down Saves (Each) Mixer Power Control (and Associated Amps) Saves MIC_BIAS Powered Down Saves2 2 Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The 0 V and high-Z states remain unaffected by the MIC_BIAS power state. 4.5 4.5 0 0 6 6 0 0 5 3 2 0.1 mA mA mA mA |
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