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ST95010WM3TR Fiches technique(PDF) 6 Page - STMicroelectronics |
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ST95010WM3TR Fiches technique(HTML) 6 Page - STMicroelectronics |
6 / 18 page Write Status Register (WRSR) The WRSR instruction allows the user to select the size of protected memory. The user may read the blocks but will be unable to write within the pro- tected blocks. The blocks and respective WRSR control bits are shown in Table 4. When the WRSR instruction and the 8 bits of the Status Register are latched-in, the internal write cycle is then triggered by the rising edge of S. This rising edge of S must appear no later than the 16th clock cycle of the WRSR instruction of the Status Register content (it must not appear a 17th clock pulse before the rising edge of S), otherwise the internal write sequence is not performed. Read Operation The chip is first selected by putting S low. The serial one byte read instruction is followed by a one byte address (A7-A0), each bit being latched-in during the rising edge of the clock (C). Bit 3 (see Table 3) of the read instruction contains address bit A8 (most significant address bit). Then the data stored in the memory at the selected addressis shifted out on the Q output pin; each bit being shifted out during the falling edge of the clock (C). The data stored in the memory at the next address can be read in sequence by continuing to provide clock pulses. The byte address is automatically incre- mented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0h allow- ing the read cycle to be continued indefinitely. The read operation is terminated by deselecting the chip. The chip can be deselectedat anytime during data output. Any read attempt during a write cycle will be rejected and will deselect the chip. C D AI01440 S Q A7 2 1 3 4 5 6 7 8 9 10 1112 131415 1617 1819 A6 A5 A4 A3 A2 A1 A0 A8 20 21 22 23 765 43 2 0 1 HIGH IMPEDANCE DATA OUT INSTRUCTION BYTE ADDRESS 0 Figure 6. Read Operation Sequence Status Register Bits Protected Block Array Address Protected BP1 BP0 ST95040 ST95020 ST95010 0 0 none none none none 0 1 Upper quarter 180h - 1FFh C0h - FFh 60h - 7Fh 1 0 Upper half 100h - 1FFh 80h - FFh 40h - 7Fh 1 1 Whole memory 000h - 1FFh 00h - FFh 00h - 7Fh Table 4. Write Protected Block Size Notes: A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040. 6/18 ST95040, ST95020, ST95010 |
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