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ST95P08B3TR Fiches technique(PDF) 1 Page - STMicroelectronics |
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ST95P08B3TR Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 16 page AI01256 S VCC ST95P02 HOLD VSS W Q C D Figure 1. Logic Diagram ST95P02 SERIAL ACCESS SPI BUS 2K (256 x 8) EEPROM NOT FOR NEW DESIGN 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE 3V to 5.5V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE 2 MHz CLOCK RATE MAX BLOCK WRITE PROTECTION STATUS REGISTER 16 BYTE PAGE MODE WRITE PROTECT SELF-TIMED PROGRAMMING CYCLE E.S.D.PROTECTION GREATER than 4000V The ST95P02 will be replaced shortly by the updated version ST95020 DESCRIPTION The ST95P02 is a 2K bit Electrically Erasable Programmable Memory (EEPROM) fabricated with SGS-THOMSON’s High Endurance Single Polysili- con CMOS technology. The 2K bit memory is or- ganised as 16 pages of 16 bytes. The memory is accessed by a simple SPI bus compatible serial interface. The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q). The device connected to the bus is selected when the chip select input (S) goes low. Commu- nications with the chip can be interrupted with a hold input (HOLD). The write operation is disabled by a write protect input (W). C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground Table 1. Signal Names 8 1 SO8 (M) 8 1 PSDIP8 (B) 0.25mm Frame June 1996 1/16 |
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