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ST70136B Fiches technique(PDF) 8 Page - STMicroelectronics |
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ST70136B Fiches technique(HTML) 8 Page - STMicroelectronics |
8 / 24 page ST70136 8/24 4 - FUNCTIONAL DESCRIPTION 4.1 - General The ST70136 consists of the following functional blocks: – Transmit Signal Path – Receive Signal Path – Bias Voltage and Current Generation – Digital Data Interface – Control Serial Interface – Tone Detector – Power Down mode management 4.2 - Transmit Path Description The transmit path contains the 14-bit digital to analog converter (DAC) necessary to generate the transmit signal from a 16-bit digital input word. This transmit signal is then scaled by the on chip programmable gain amplifier (TxPGA) from 0 to -15dB in 1dB steps. The scaled output signal is then driven off chip to the external filters and power amplifier (PA) which drives the DMT signal to the subscriber loop. The transmit path is fully differential. 4.3 - Receive Path Description The receive path contains first an attenuator (which allows the selection between 4 attenuated versions of the signal) followed by a programma- ble gain amplifier (RxPGA), a 1st order low pass anti-aliasing filter, and a 12-bit analog to digital converter (ADC). The RxPGA gain is digitally pro- grammable from 0 to 31dB in 1dB steps. The receive path is fully differential. 4.4 - VCXO The ST70136 contains the circuits required to construct an internal VCXO. It is divided in a crys- tal driver and an auxiliary 8 bits DAC for timing recovery. The crystal driver is able to operate at 35.328MHz. The DAC which is driven by the CTRLIN pin (the input of the Serial Control Interface), provides a current output with 8 bits resolution and can be used to tune the crystal frequency with the help of external components. A time constant between DAC input and VCXOUT can be introduced (via CTRLIN interface) and programmed with the help of an external capacitor (on VCOCAP pin). 4.5 - Bias Voltage and Current Generation The bias circuitry contains a bandgap voltage ref- erence from which the converters references and analog ground voltages are generated. This block also generates an accurate bias current using an external resistor. 4.6 - Digital Data Interface To facilitate data transfer between the ST70136 and the digital data pump, a 4-bit wide serial inter- face for the transmit and receive path is incorpo- rated into the AFE. This interface consists of four transmit pins (TX[0:3]), four receive pins (RX[0:3]), and the nec- essary control signals (CLKM, CLKWD) to trans- mit and receive the required data. |
Numéro de pièce similaire - ST70136B |
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Description similaire - ST70136B |
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