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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TDA7590 Fiches technique(PDF) 8 Page - STMicroelectronics |
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TDA7590 Fiches technique(HTML) 8 Page - STMicroelectronics |
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8 / 40 page  Pin description TDA7590 8/40 51 HAD[7] I/O Host 8-bit data line 7. Host Data Bus and/or address lines when in multiplexed mode. 52 HAD[6] I/O Host 8-bit data line 6. Host Data Bus and/or address lines when in multiplexed mode. 53 HAD[5] I/O Host 8-bit data line 5. Host Data Bus and/or address lines when in multiplexed mode. 54 HAD[4] I/O Host 8-bit data line 4. Host Data Bus and/or address lines when in multiplexed mode. 55 COREVDD I Core Power Supply. 56 COREVSS I Core Ground. 57 HAD[3] I/O Host 8-bit data line 3. Host Data Bus and/or address lines when in multiplexed mode. 58 HAD[2] I/O Host 8-bit data line 2. Host Data Bus and/or address lines when in multiplexed mode. 59 HAD[1] I/O Host 8-bit data line 1. Host Data Bus and/or address lines when in multiplexed mode. 60 HAD[0] I/O Host 8-bit data line 0. Host Data Bus and/or address lines when in multiplexed mode. 61 AA[3] O Address Attributes line 3.Port A address attributes/chip select pins with programmable polarity. 62 AA[2] O Address Attributes line 2.Port A address attributes/chip select pins with programmable polarity. 63 BR_N O Bus Request. Asserted when Port A requires bus mastership to perform off- chip accesses. 64 BB_N I/O Bus Busy. Asserted by Port A when bus_busy_in_n is negated and BG_N is asserted. 65 IOVDD I IO Power Supply. 66 IOVSS I IO Ground. 67 WEN_N O Write Enable. 68 OEN_N O Output Enable. 69 AA[1] O Address Attributes line 1.Port A address attributes/chip select pins with programmable polarity. 70 AA[0] O Address Attributes line 0.Port A address attributes/chip select pins with programmable polarity. 71 BG_N I Bus Grant. When asserted, Port A becomes the bus master elect. Bus mastership is attained when bus busy is negated by the current bus master. 72 AB[0] O Address Bus line 0. Port A external address bus. 73 AB[1] O Address Bus line 1. Port A external address bus. 74 IOVDD I IO Power Supply. Table 1. Pin function (continued) N° Name Type Description |
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Description similaire - TDA7590 |
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