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STK14EC8-TF45 Fiches technique(PDF) 5 Page - Simtek Corporation

No de pièce STK14EC8-TF45
Description  512Kx8 Autostore nvSRAM
Download  19 Pages
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Fabricant  SIMTEK [Simtek Corporation]
Site Internet  http://www.simtek.com
Logo SIMTEK - Simtek Corporation

STK14EC8-TF45 Fiches technique(HTML) 5 Page - Simtek Corporation

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STK14EC8
5
Simtek Confidential
Jan, 2008
Document Control #ML0060 Rev 1.1
Preliminary
SRAM READ CYCLES #1 & #2
Note c:
W must be high during SRAM READ cycles.
Note d:
Device is continuously selected with E and G both low
Note e:
Measured
± 200mV from steady state output voltage.
Note f:
HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
SRAM READ CYCLE #2: E and G Controlledc,f
NO.
SYMBOLS
PARAMETER
STK14EC8-15
STK14EC8-25
STK14EC8-45
UNITS
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
tELQV
tACS
Chip Enable Access Time
15
25
45
ns
2
tAVAV
c
tELEH
c
tRC
Read Cycle Time
15
25
45
ns
3
tAVQV
d
tAVQV
d
tAA
Address Access Time
15
25
45
ns
4
tGLQV
tOE
Output Enable to Data Valid
10
12
20
ns
5
tAXQX
d
tAXQX
d
tOH
Output Hold after Address Change
3
3
3
ns
6
tELQX
tLZ
Address Change or Chip Enable to
Output Active
3
3
3
ns
7
tEHQZ
e
tHZ
Address Change or Chip Disable to
Output Inactive
7
10
15
ns
8
tGLQX
tOLZ
Output Enable to Output Active
0
0
0
ns
9
tGHQZ
e
tOHZ
Output Disable to Output Inactive
7
10
15
ns
10
tELICCH
b
tPA
Chip Enable to Power Active
0
0
0
ns
11
tEHICCL
b
tPS
Chip Disable to Power Standby
15
25
45
ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQ X
ST AND BY
DAT A VAL ID
4
tGL QV
DQ (D ATA OUT)
E
ADDR ESS
G
ICC
AC T IVE
10
tELI CC H
11
tEHI CC L
7
tEHQ Z
8
tGL QX
1
tEL Q V
9
tGH Q Z
2
tELEH
29
tEHAX
3
tAV QV
27


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