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STK11C88-SF25I Fiches technique(PDF) 4 Page - Simtek Corporation |
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STK11C88-SF25I Fiches technique(HTML) 4 Page - Simtek Corporation |
4 / 16 page 4 Jan, 2008 Document Control #ML0012 Rev 2.0 STK11C88 SRAM READ CYCLES #1 & #2 (VCC = 5.0V + 10%) Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g SRAM READ CYCLE #2: E and G Controlledf NO. SYMBOLS PARAMETER STK11C88-25 STK11C88-45 UNITS #1, #2 Alt. MIN MAX MIN MAX 1 tELQV tACS Chip Enable Access Time 25 45 ns 2 tAVAV f , tELEH f tRC Read Cycle Time 25 45 ns 3 tAVQV g tAA Address Access Time 25 45 ns 4 tGLQV tOE Output Enable to Data Valid 10 20 ns 5 tAXQX g tOH Output Hold after Address Change 5 5 ns 6 tELQX tLZ Address Change or Chip Enable to Output Active 5 5 ns 7 tEHQZ h tHZ Address Change or Chip Disable to Output Inactive 10 15 ns 8 tGLQX tOLZ Output Enable to Output Active 0 0 ns 9 tGHQZ h tOHZ Output Disable to Output Inactive 10 15 ns 10 tELICCH e tPA Chip Enable to Power Active 0 0 ns 11 tEHICCL d, e tPS Chip Disable to Power Standby 25 45 ns DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV 6 tELQ X ST AND BY DAT A VAL ID 4 tGL QV DQ (D ATA OUT) E ADDR ESS G ICC AC T IVE 10 tELI CC H 11 tEHI CC L 7 tEHQ Z 8 tGL Q X 1 tEL Q V 9 tGH Q Z 2 tELE H 29 tEHAX 3 tAV QV 27 |
Numéro de pièce similaire - STK11C88-SF25I |
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Description similaire - STK11C88-SF25I |
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