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TDA7333NTR Fiches technique(PDF) 11 Page - STMicroelectronics |
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TDA7333NTR Fiches technique(HTML) 11 Page - STMicroelectronics |
11 / 36 page TDA7333N Functional description 11/36 3 Functional description 3.1 Overview The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip. It recovers the inaudible RDS/RBDS information which are transmitted on most FM radio broadcasting stations. The oscillator frequency can be derived from the tuner with typical value of 10.25 MHz . The device can operate with frequencies in the range of 4-21 MHz. Therefor the fractional PLL must be initialized through I2C/SPI interface to generate the internal 8.55 MHz or 8.664 MHz reference clock with a freq. tolerance of ±0.7 kHz. Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all further processing is done in the digital. After filtering the highly over sampled output of the A/D converter, the RDS/RBDS demodulator extracts the RDS data clock, RDS data signal and the quality information. A next RDS/RBDS decoder will synchronize the bit wise RDS stream to a group and block wise information. This processing includes an error detection and error correction algorithm. In addition, an automatic flywheel control avoids overheads in the data exchange between the RDS/RBDS processor and the host. The device operates in accordance with the CENELEC Radio Data System (RDS) specification EN50067. 3.2 Fractional PLL Figure 3. Fractional PLL Phase Comperator & VCO Input Divider Output Divider Fractional Divider PLL Controller Mux f(vco) |
Numéro de pièce similaire - TDA7333NTR |
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Description similaire - TDA7333NTR |
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